CL|WCL|RTL performance (SB) : 32M scaling charts : PSC WCL > CL performance bug

[cheapseats]

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This project is looking at CL-based performance and scaling on Sandybridge, taking into account the effects of CL/WCL/RTL.

The aim is to give meaningful context to CL performance and performance change, based on testing and observation.

For quick reference, see tables in Post 2. The tables briefly summarise the contents of Posts 3 and 4.

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CL = CAS Latency

WCL = CAS Write Latency (also known as CWL or WL)

RTL = Round Trip Latency


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Index
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Post 1 :

• Index.

Post 2 :

• Hyper & PSC : CL and WCL scaling tables for RTL, vDIMM, AIDA Read/Latency, 32M ranking.

Post 3 :

• PSC WCL > CL performance bug.

Post 4 :

• Hyper & PSC : CL/WCL/RTL 32M performance scaling @ x-10-7-26 (direct comparison timing & subtiming).

• table+chart format to show setting-to-setting scaling for CL/WCL/RTL changes.

• 32M + AIDA screenshots.

Post 5 :

• Hyper : CL10 to CL6 1067/933/800 32M performance scaling @ x-7-5-20 + optimal WCL.

• charts and 32M + AIDA screenshots.

Post 6 : reserved.


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by cheapseats 2011-2012.