Radeon HD 7000 Revealed: AMD to Mix GCN with VLIW4 & VLIW5 Architectures

[LordEC911]

http://www.obr-hardware.com/

Update, July 27, 2011:

Something has been happening with increasing frequency that needs to stop: linking or referring to the work of banned members (whether that's to their posts on another forum or to a site/blog they now run). This is a forum-wide rule but is of particular concern in the News Section where first infraction = temporary forum ban and permanent News Section ban.

Some banned members leak early hardware benchmarks or roadmaps that may seem important, but when somebody has been removed from XS, they no longer have a right to have a voice on XS.

We realize not all banned members are known to all current members so this may not always result in an infraction, it depends on the situation and recent in-thread warnings.

http://www.xtremesystems.org/forums/...=1#post4914806

[hurleybird]

32 ROPS, yeah, I don't think so.

[generics_user]

i just can't take this guy seriously; there isn't any other site out there spreading more hate against single hardware manufacturers than his blog; even apple haters don't go that far

[bill_d]

i just can't take this guy seriously; there isn't any other site out there spreading more hate against single hardware manufacturers than his blog; even apple haters don't go that far

this

what did AMD do to him crap in his oatmeal
charlie with nv is not this bad

[tbone8ty]

hopefully they will have nice cooling solution under that hood

http://videocardz.com/29546/amd-rade...hamber-cooling

[paulbagz]

Yargh OBR.

-PB

[SKYMTL]

I am not saying whether the OBR post is right or absolutely wrong but what about it strikes you as being anti-AMD?

[tbone8ty]

what would higher or lower ROPs do? ive seen 64, 48, now 32 floating around.

hypothetically speaking say the SP are 2048 and texture units are 128. can u determine the ROPS from that?

this table seems to be more like the 7970 and 7950 specs mixed together

[DilTech]

what would higher or lower ROPs do? ive seen 64, 48, now 32 floating around.

hypothetically speaking say the SP are 2048 and texture units are 128. can u determine the ROPS from that?

this table seems to be more like the 7970 and 7950 specs mixed together

Rops are tied to the memory controller, in blocks of 4-8 rops per memory bus channel (usually 8 these days). 32 rops would be either a 256bit bus or a 512bit bus. For 384-bit it'd either be 24 or 48 rops. You can't divide 32 rops evenly to make said 384-bit bus, and as such it's probably fake just based off of that alone.

[Lanek]

what would higher or lower ROPs do? ive seen 64, 48, now 32 floating around.

hypothetically speaking say the SP are 2048 and texture units are 128. can u determine the ROPS from that?

this table seems to be more like the 7970 and 7950 specs mixed together

The TMU are easy to calculate, there's 4 TMU/CU ..., 32x4. Untill they want double the number and end with 256 ( who will be innefficient anyway )

For the ROPS, well Diltech have said all.

I add just a little quote from Anandtech GCN article:

After a trip through the CUs, graphics work then hits the pixel pipelines, which are home to the ROPs. As it’s customary to have a number of ROPs, there will be a scalable number of pixel pipelines in GCN; we expect this will be closely coupled with the number of memory controllers to maintain the tight ROP/L2/Memory integration that’s so critical for high ROP performance.

and more who have absolutely nothing to do with ROP

On the other side of the coin we have the graphics hardware. As with Cayman a graphics command processor sits at the top of the stack and is responsible for farming out work to the various components of the graphics subsystem. Below that Cayman’s dual graphics engines have been replaced with multiple primitive pipelines, which will serve the same general purpose of geometry and fixed-function processing. Primative pipelines will be responsible for tessellation, geometry, and high-order surface processing among other things. Whereas Cayman was limited to 2 such units, GCN will be fully scalable, so AMD will be able to handle incredibly large amounts of geometry if necessary.

We have all see thoses pictures allready, but this can help for see exactly how it work

[DilTech]

Nice to see AMD are taking my primary complaint about their last architecture seriously and giving this one a big push in it's ability to perform tessellation. In a lot of ways Cayman and Cypress were DX10.1 cards with DX11 kind of tacked on competing against cards made for DX11 from the ground up.

It'll be interesting to see AMD with their true next generation architecture, since it'll be their first big change since the HD2900. Going to VLIW4 from VLIW5 was a step in the right direction--but, it wasn't nearly as drastic of a change as a lot of people here made it out to be.

[SKYMTL]

Rops are tied to the memory controller, in blocks of 4-8 rops per memory bus channel (usually 8 these days). 32 rops would be either a 256bit bus or a 512bit bus. For 384-bit it'd either be 24 or 48 rops. You can't divide 32 rops evenly to make said 384-bit bus, and as such it's probably fake just based off of that alone.

Remember, AMD never "scaled" their cache, ROP and memory hierarchy like NVIDIA did. With NVIDIA all three were tied together due to the nature of their core architecture but AMD could always scale them in an asymmetric fashion.

For example, the Barts LE core used on the HD 6790 1GB disabled two of the Render Back Ends of the Barts core to produce a card with a 256-bit memory bus but only 16 ROPs (rather than 32). As such, PAST AMD cores weren't tied down in the same way as NVIDIA's Fermi architecture.

[STEvil]

On a related note, there is a way to have uneven/mismatched numbers of rops/etc as well, but I dont think we'll be seeing it this round of GPU's. To put it simply: kal-el.

[Lanek]

Remember, AMD never "scaled" their cache, ROP and memory hierarchy like NVIDIA did. With NVIDIA all three were tied together due to the nature of their core architecture but AMD could always scale them in an asymmetric fashion.

For example, the Barts LE core used on the HD 6790 1GB disabled two of the Render Back Ends of the Barts core to produce a card with a 256-bit memory bus but only 16 ROPs (rather than 32). As such, PAST AMD cores weren't tied down in the same way as NVIDIA's Fermi architecture.

I agree, but let#s not forget we dont speak about a low end card who was a cutted Barts core. But well, its not really important anyway.

[LordEC911]

On a related note, there is a way to have uneven/mismatched numbers of rops/etc as well, but I dont think we'll be seeing it this round of GPU's. To put it simply: kal-el.

Are they using similar memory controllers?

[DilTech]

Remember, AMD never "scaled" their cache, ROP and memory hierarchy like NVIDIA did. With NVIDIA all three were tied together due to the nature of their core architecture but AMD could always scale them in an asymmetric fashion.

For example, the Barts LE core used on the HD 6790 1GB disabled two of the Render Back Ends of the Barts core to produce a card with a 256-bit memory bus but only 16 ROPs (rather than 32). As such, PAST AMD cores weren't tied down in the same way as NVIDIA's Fermi architecture.

That's going with the 4 split rather than the 8 split, still matches the mathematics we've always seen. They didn't disable RBE's, they disabled half of the Rops per RBE.

I seriously can't even remember the last time we saw a gpu that wasn't symmetrical rop to memory controller. In fact, I'm now curious... When IS the last time AMD/ATi released a chip that wasn't? (serious question) AFAIK both brands ARE actually tied together in this aspect presently.

[hurleybird]

Everyone keeps saying 32CUs and 2048 ALUs.... but that's not counting the scalar units. So why not advertise as an 2080 ALU part? Or are the scalar ALUs only there for GPGPU?

[mR Yellow]

We want benches already.

[Lanek]

Everyone keeps saying 32CUs and 2048 ALUs.... but that's not counting the scalar units. So why not advertise as an 2080 ALU part? Or are the scalar ALUs only there for GPGPU?

I think it's a little bit complicate to include it.. basically, the Scalar unit is there for take some operation for dont charge the SMID with them, (" specifically, simple integer operations to control flow operations like conditional branches (if/else) and jumps, and in certain cases read-only memory operations from a dedicated scalar L1 cache. Overall the scalar unit can execute one instruction per cycle, which means it can complete 4 instructions over the period of time it takes for one wavefront to be completed on a SIMD. (copied from anandtech article) "on/off mathematicals op" .

Let say it is not responsible of the same part of the vertex Alu, or SP ... Dunno if they count it or not. It's a little bit like the tesselation engine, hard to count them in the SP. GPU become more and more complex, and i think the SP numbers is just purely indicative for get an idea of the spec now.

[Pokerface]

Will the 7000 series be dx 11.1?

[zanzabar]

Will the 7000 series be dx 11.1?

it should as its a minor update to accommodate the win8 driver model and lower quality color support (the end of the 24bit minimum), i would assume that all the amd and NV dx11 cards will work with dx11.1 with driver updates.

[Pokerface]

Thank you zanzabar.

[Olivon]

AMD: We Are Shipping Our 28nm GPUs Now - XBitLabs

"We are ramping 28nm [products] with TSMC in Taiwan and shipping the products here and now. We are very excited about the products," said Rory Read, chief executive officer of AMD, during IT Supply Chain conference organized by Raymond James.

[cx-ray]

I just read that the idle power is advertised at 3W for the HD 7970. Very nice especially for those running multiple cards.

[Olivon]

Fuad talks about 365mm² regarding chip size :

The chip is 365 square millimeters in size and performance wise it should end up faster than Geforce GTX 580.

http://www.fudzilla.com/graphics/ite...ent-in-january