cache size, binning, and overclocking potential of SB-E

[Mr. Headshot]

So Intel made several sandy bridge models with 6MB L3, and several with 8MB L3, and the K models were the top bin of each.

Did they print two different patterns for the two different cache sizes, or print one pattern and disable 1/4 of the cache in some of them?

Now for sandy bridge E, there's going to be only one model number for each cache size. If they're printing three different patterns, then instead of getting the top bin, we get the *only* bin, which will have much worse overclocking potential on average. Or are they really all printed on the same wafers from the same pattern, then binned, then crippled by disabling part of the cache? If the latter, would there be any way of re-enabling the extra cache?

[Computurd]

will there be a difference between the mid range with 12m cache and the high range with 15m cache? that is my big question, how much of a difference between the two chips?

[Mr. Headshot]

3960X vs 3930K could go either way. The extreme edition has that slightly larger cache and slightly higher stock speed. If they're manufactured separately, then the one with the smaller cache might overclock higher. If they're manufactured from the same pattern, then binned & cache-disabled, the extreme edition will overclock higher. But it won't be a big enough difference to justify the extra $500 that I could save and upgrade to ivy bridge in a few months (assuming they don't mess up the die shrink like Thoroughbred-A... they're using funky new 3D gates)