So Intel made several sandy bridge models with 6MB L3, and several with 8MB L3, and the K models were the top bin of each.

Did they print two different patterns for the two different cache sizes, or print one pattern and disable 1/4 of the cache in some of them?

Now for sandy bridge E, there's going to be only one model number for each cache size. If they're printing three different patterns, then instead of getting the top bin, we get the *only* bin, which will have much worse overclocking potential on average. Or are they really all printed on the same wafers from the same pattern, then binned, then crippled by disabling part of the cache? If the latter, would there be any way of re-enabling the extra cache?