AMD FX-8150 Bulldozer finally tested

[mav2000]

Still not here in India as well...whats the price in SG?

[nn_step]

The Integer performance seems rather unusual especially when looking at the decode rate. I've found some edge cases where the decode rate seems to be only 1 instruction per clock [All of them thus far seem to be in Compatibility mode and Legacy mode]

[haylui]

Still not here in India as well...whats the price in SG?

Since the shop is giving out bundle price, so not accurate to tell it in processor only price
When the processor bundle with Asus Crosshair V Formula
FX-4100 $490 (~US$386)
FX-6100 $572 (~US$451)
FX-8120 $612 (~US$482)
FX-8150 $667 (~US$525)

the price above is in Singapore Dollar
converting to USD would be 1 SGD to 0.789 USD

link: http://assets.hardwarezone.com/retai...11%20new_0.pdf

[haylui]

The Integer performance seems rather unusual especially when looking at the decode rate. I've found some edge cases where the decode rate seems to be only 1 instruction per clock [All of them thus far seem to be in Compatibility mode and Legacy mode]

how do you found that?
since BD is sharing 4 instruction fetch/decoder across 2 cores in a module, and the fetch/decoder is shared at alternate clock. Effectively per core has just 4/2 fetch/decoder's peak performance.

[kl0012]

FX-4100 Linux review
http://www.phoronix.com/scan.php?pag...ulldozer&num=1

The AMD FX-4100 is currently carrying a retail price of about $130 USD while the Intel Core i3 2120 is coming in right now at $140 USD. In most of the Linux tests that were carried out, this lower-end Sandy Bridge CPU blew AMD's FX-4100 out of the water. The i3-2120 operates at just 3.3GHz and is a dual-core part with Hyper Threading while the FX-4100 operates at 3.6/3.8GHz and is a true quad-core.

[nn_step]

how do you found that?
since BD is sharing 4 instruction fetch/decoder across 2 cores in a module, and the fetch/decoder is shared at alternate clock. Effectively per core has just 4/2 fetch/decoder's peak performance.

By experimenting with a couple synthetic benchmarks and assembly programs.

here is the complete list:
AAA - ASCII adjust AL after addition
AAD - ASCII adjust AX before division
AAM - ASCII adjust AX after multiplication
AAS - ASCII adjust AL after subtraction

Which Ironically are only valid in in Compatibility mode and Legacy mode; rarely used and thus probably a non-issue.

Now testing to see if it is just a Bulldozer or general x86 issue.

[Russian]

http://semiaccurate.com/2011/10/17/w...er-underwhelm/

http://semiaccurate.com/2011/10/17/b...ingle-problem/

Interesting read

I'm pretty sure those are going to say what I said in my review, but perhaps with a little more bias. Plus, Has charlie actually reviewed Bulldozer? I don't think so...?

[Dresdenboy]

By experimenting with a couple synthetic benchmarks and assembly programs.

here is the complete list:
AAA - ASCII adjust AL after addition
AAD - ASCII adjust AX before division
AAM - ASCII adjust AX after multiplication
AAS - ASCII adjust AL after subtraction

Which Ironically are only valid in in Compatibility mode and Legacy mode; rarely used and thus probably a non-issue.

Now testing to see if it is just a Bulldozer or general x86 issue.

These are microcoded instructions.

But there are many rules, like 1 store/cycle etc. Try rows of push/pop (found a lot in SuperPi's code, slowing it down, besides hardly OOO executable FP code).