And the Bulldozer die size is……

[Tenknics]

Doesn't matter. Their current lineup is even bigger and not competitive at all.

They probably saved R&D and drawing costs to keep it like this... and those saved costs probably are alot more profitable then the volume in which BD will ship.

Apples and oranges. 4 BD modules are not the same as 4 SB cores. You could say that this BD die is an 8 core design.

In the end thats also pretty much irrelevant and its performance what counts

I wonder how much an 8-core SB would take, without IGP. Then again BD isn't full 8-core, so it's hard to compare the die sizes. In any case performance is what matters for the customer. If AMD needs a 315 mm^2 to compete with a 216 mm^2 chip including graphics portion it doesn't bode well.

Well you see how this turns out /financial wise) in the margins.

I thought it'd be previous obvious to connect the dots on this board, but there was a reason I mentioned that.

Sure it's all about performance, but it's also about price/performance. Amd is having to make a bigger chip to compete with Intel. Die size costs money, something that AMD does not have in excess quantity to burn right now. Bigger die size, less chips per wafer, cost per chip goes up and margins, if any are left, go down...

A full-sized quad-core SB is 216 mm^2, is only 68% of the size of this monster, and that's with IGP.

6-core westie CPU is only 239 mm^2, and AMD is not even positioning the 8-core chips against Intel’s 6 core chips right now.

It will cost AMD substantially more to make a Bulldozer chip that will be sold at or below the price of a much smaller Intel chip…. AMD will not be making much if any profit off these chips in the desktop.

Math never lies...

2 Westmere Cores > 1 BD module

And die size?
2 westmere cores = 1 BD module


Hence my uh oh.

[TESKATLIPOKA]

crazydiamond yep, if you have a 4 module cpu and an application using 4 threads, then each thread is executed in different module.

[TESKATLIPOKA]

Tenknics

And die size?
2 westmere cores = 1 BD module

Are you kidding?
One westmere core is between 13-15mm2 excluding 256KB L2 cache. BD is only 18-19mm2 excluding 2MB L2 cache for both integer klusters. So where is your 2 Intel cores = 1 BD module?
Thats just cache which can be cut down to 1/4 or 1/8 with some performance penalty if they wanted.
I found only the comparison between SB and BD
http://imageshack.us/photo/my-images...soncrp7cr.png/

edit: http://www.overclockers.com/forums/a.../t-550542.html look at Agena, the size is a bit smaller though compared to BD or you can calculate it
you can see even if they have a larger die, they still have a decent margin on them, not like Intel but still way better than you think.
Even on Thuban they have dollars and is bigger but cheaper than BD.

[Manicdan]

on a similar thought, do you know if say the 8core BD is taking 4 threads will each thread get its own module to avoid the core performance hit when 2 threads are on a module? or would it just give the 4 threads to 2 modules & shut off other 2 and turbo the 2 in use?

based on this post by flanker:

next slides from Hotchips


http://img577.imageshack.us/i/a5464736s.jpg

the only way to get past the all core turbo is to have half the modules turned off, and that will give about another 500mhz we believe (if rumor that 1.0ghz turbo is real)

without actual clocks and actual perf loss from a module sharing threads its not possible to determine the best option.
but basically its this: if the second turbo (black bars) is able to provide more perf while sharing the threads, than the first turbo (red bars) is able to when threads are independent. then the shared method would be best for perf, and most likely perf per watt too.

i would love if we had the option to control this through AOD. if a game needs one really fast thread, and then a few weaker threads, it would be the best benefit to give the strongest threads to its own module, then let the others share as needed, and use dynamic turbo so one is boosted to the max, while the others might still be running at whatever clock rates are needed, even if it cannot shut of half the modules, it should still be under the max tdp.

in the future with perfect fusion and perfect turbo, a chip will be able to utilize 100% usage by adjusting clocks to match the exact needs of the application. i doubt we will ever reach this perfect utopia, but how close we get is definitely something worth watching

[JumpingJack]

crazydiamond yep, if you have a 4 module cpu and an application using 4 threads, then each thread is executed in different module.

Ideally this would be the case but in reality is often not true. Thread scheduling is performed by the os and not done by the processor. Win 7 has improved scheduling tremendously for asymmetric execution resources but it is still not perfect.

[Sparky]

Yeah, 2 Sandybridge cores would beat 6 of AMD's in gaming so if BD has 8 they should be able to take on 2 easily.

[TESKATLIPOKA]

JumpingJack then its enough if AMD releases some OS update for schedulling and the performance will go up.

[Manicdan]

there was talk about AMD working with MS about the scheduler.

[JumpingJack]

JumpingJack then its enough if AMD releases some OS update for schedulling and the performance will go up.

AMD will not release any OS updates. It is likely (IMHO) that the SMT parking features in Win 7 are already optimized for BD as is but it is even more likely IMHO that AMD will work with MS to optimize the scheduler for BD and it will proliferate the Win Update. AMD and Intel often begin work at this level with the OS providers to prep the ecosystem for new products. For example win 7 sp1 and AVX.

[eXa]

Yeah i remember reading something about that a while ago too.
Something with keeping threads on different modules if that benefits the most, but keeping threads on the same module if sharing the resourches benefits more.

[TESKATLIPOKA]

here is a picture for some who still believe BD will perform as K10.5 in single thread at the same frequency
http://imageshack.us/photo/my-images...soncrp7cr.png/

without L2 cache
Llano: 9.69mm2
BD: 15.58mm2 (excluding one integer cluster) +60.8% die size
SB: 16.5mm2 +70.3% die size (+6% compared to BD module without the second integer cluster, everything else in module can be used by a single integer cluster)

[Gautam]

the greater amount of empty space is probably due to heavier use of synthesized logic and auto place and route instead of manual custom layout. That pic probably grossly misrepresents it though...probably mostly wiring in what looks like empty space.

[TESKATLIPOKA]

JumpingJack then maybe it's included I don't know, I just remember AMD has some OS update for Athlon X2 some years ago although I don't remember what for.

edit: I have read your whole post and yes if not AMD update then it will be present in windows 7 SP1

[Hornet331]

What you mean was the dualcore optimizer, and it was for fixing sync errors in some games.

And again in the end it doesn't matter who has the smaller core, more cores per cpu or whatever. If intel delivers the same performance with a quadcore that is smaller and amd needs a octacore that is larger this reflects on the margins both get for this chips. For the consumer itself this is pretty much irrelevant.

[TESKATLIPOKA]

Hornet331 you are right, but as you can see some people still think its pretty important.

I would like to see how good it is in programs using at least 8 threads, because only then you will see why its so much bigger.

[Chaserjzx100]

all of this talk just for the empty space of that supposedly BD die shot from a website named semi accurate :/

[TESKATLIPOKA]

Chaserjzx100 we need to do something, still some time left before the release.

[informal]

on a similar thought, do you know if say the 8core BD is taking 4 threads will each thread get its own module to avoid the core performance hit when 2 threads are on a module? or would it just give the 4 threads to 2 modules & shut off other 2 and turbo the 2 in use?

AFAIK it should work like that. Threads go to separate modules first then after n=5 in thread count it gets assigned to pairs. Similar to HT.

[Manicdan]

AFAIK it should work like that. Threads go to separate modules first then after n=5 in thread count it gets assigned to pairs. Similar to HT.

and what happens when it wants to turbo one of those threads? unless it shuts off half the modules, it wont turbo all the way

[informal]

and what happens when it wants to turbo one of those threads? unless it shuts off half the modules, it wont turbo all the way

Well at least in the case of fp heavy code it makes case.If the fp heavy code is less than 5 threads then 4 cores will use full flexfp. I have no idea how Turbo works into all of this.

[TESKATLIPOKA]

informal if I remember correctly FPU doesn't have any turbo.

[highoctane]

The size is largely irrelevant to the end user, price/performance sets the bar.

If AMD can get back in gear in the server market with BD the margins there should be able to offset the skinnier consumer margins and things should potentially avg out.

[AliG]

here is a picture for some who still believe BD will perform as K10.5 in single thread at the same frequency
http://imageshack.us/photo/my-images...soncrp7cr.png/

without L2 cache
Llano: 9.69mm2
BD: 15.58mm2 (excluding one integer cluster) +60.8% die size
SB: 16.5mm2 +70.3% die size (+6% compared to BD module without the second integer cluster, everything else in module can be used by a single integer cluster)

No one believes that BD won't surpass k10.5 in ipc, hell just look at my signature and you'll see that I also find that possibility to be absurd. That's the not the issue.

The problem is that Intel has denser cache (with considerably lower latency) so they can squeeze out more performance within the same amount of space as an AMD. When factor in the way the bulldozer pipeline is designed, it has to run at a very high frequency to even compete with a 2600k on a performance level - let alone SB-E. Especially considering that the biggest improvements came from reducing redundancy, it actually has fewer possible integer operations than even k8 (which had 3 2-way operators vs BD has only 4 1-way operators). So when you look at just how far behind AMD is right now, while it is a huge accomplishment for them close the gap, it's also incredibly unlikely that they will actually supersede Intel in the ipc department. And yes, that does matter very much because as Jack mentioned windows 7 just isn't optimized enough to take full advantage of BD's module system and in all reality neither will windows 8.

Bulldozer will be best served as a server product. I don't get why people think it will magically be a great gaming cpu; it's just not designed to do that. For that route still even a 2500k will be a better option. This is why die size is such a big deal, considering that the market they are competing into places great emphasis on performance per watt they need to reduce as much possible transistor leakage as possible and the best way to do that is to simply shorten the pipelines.

At this point in time, AMD's best bets are with llano and the servers. Llano is a hell of a cpu and quite frankly far exceeded many expectations despite coming very late. I can't wait to get a laptop based off that platform. However when it comes to desktops I feel absolutely zero buyers remorse right now, if anything I'm more disappointed in myself for waiting so long.

[eXa]

edit: I have read your whole post and yes if not AMD update then it will be present in windows 7 SP1

W7 SP1 has been out for almost half a year already....

[gosh]

The problem is that Intel has denser cache (with considerably lower latency)

It is higher clocked on Intel. Intel is also using prefetching to the L2 cache. BD will do that too, Phenom doesn't