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Thread: SSD Write Endurance 25nm Vs 34nm

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    Quote Originally Posted by Computurd View Post
    lol send it to me! i have 8 256 GB C300, but they are on an open loan from Crucial, i dont think they would appreciate me killing one! actually maybe i should ask permission to do so. i will see what i can do
    LOL I wish I could give it to you guys but I have not decided on a SSD to buy yet and was thinking about a C300 ( not M4 because of 25nm NAND) and wondered how its endurance is etc. As endurance is key to me and other people I would tell micron this :

    Let us do this endurance test on one of your 8 c300 to get more sales as people can see endurance is good etc.

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    123tb. 37%.

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    as thinking about a C300 ( not M4 because of 25nm NAND)
    thats a terrible reason not to buy a M4, and this thread that you are posting in shows why! You will probably be better in the long run with 25nm. better tech!
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    Quote Originally Posted by Computurd View Post
    thats a terrible reason not to buy a M4, and this thread that you are posting in shows why! You will probably be better in the long run with 25nm. better tech!
    We don't know yet... the media wear indicator is hardly something we can trust at this point in time.

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    Quote Originally Posted by One_Hertz View Post
    We don't know yet... the media wear indicator is hardly something we can trust at this point in time.
    Well, we know that in at least one sample it is good enough to survive 123 TB of writes to an SSD with 40GiB of flash, which comes to 2863 erase cycles on average.

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    Quote Originally Posted by Computurd View Post
    thats a terrible reason not to buy a M4, and this thread that you are posting in shows why! You will probably be better in the long run with 25nm. better tech!
    Conventional tech wisdom, based on the nature of how flash NAND works, holds that memory cells at 34nm can be written to more times than memory cells at 25nm. I have yet to see anything in this testing that contradicts that. All the testing has shown so far is that 25nm cells can last longer than the typical 3000 p/e c. estimate. So far only 6 TB longer, but longer nevertheless. Without some sort of modification to the technology, I don't expect that the laws of physics relating to floating gate transistors are going to be all that open to negotiation. What I expect this testing to show is that the traditional estimates based on process size are more or less wild-assed guesses.

    Toshiba is supposed to be producing both 2 bit and 3 bit per cell 19nm MLC flash NAND by the end of the year. We can only hope that the 3 bit per cell MLC will not end up in SSDs. IMFT is also supposed to be producing 20nm 2 and 3 bit per cell MLC flash NAND by the end of the year. The old write estimates for that process size were around 1500 p/e cycles, but of course neither company is going to be using those estimates. Instead the write endurance estimates are exactly the same as for 25nm cells. What that shows is not that these companies can get around the laws of physics, but that, without testing, they can claim anything they want which serves their marketing purposes.

    You may argue that writes to the 25nm memory are already so high that it is not a concern to the average user and that may very well be true, but not everyone is the average user, and some people might like to get more value for their money in terms of a device capable of having more data written to it. Probably a lot more, but we will see. To me, assuming equal write amplification, a 34nm flash NAND device is worth more than a 25nm one. It offers greater value. It is superior technology in the same way that a 22nm CPU is superior technology to a 32nm CPU. For CPUs/GPUs smaller process size is an advantage to both the manufacturer and the end user. For flash NAND memory smaller process size is only an advantage to the manufacturer. For the end user it is inferior technology. It clearly does not do its job as well.

    In some very small consumer devices the smaller process size may be worth the tradeoff in write endurance or for mostly read only memory. But for SSDs it really only makes sense from a consumer perspective if we start to see the sort of massive, dramatic price drops that people have been predicting for years. If I am buying a device with half the write capacity it should be half the price to give the same value. That means that if a 34nm 128 GB drive is selling at $2/GB, a 25nm 128 GB drive should be selling for $1/GB. You wouldn't hear any objections from me about the process size then. But I don't think that's going to happen. Even if the full cost savings were passed on to the consumer by both the memory manufacturer and the drive manufacturer during a period of cuthroat price wars, I think the cost savings will be trivial compared to the amount of write endurance lost.

    I think that, despite process shrinks, memory prices will continue to be market driven and will fluctuate with the market just as RAM does. Any manufacturing cost savings will be pocketed, mostly by the manufacturers themselves. If you want to get an idea of how much of the cost savings will be passed on to us from a process shrink take a look at the difference in price between a 25nm 120 GB Vertex 3 and the 32nm Max IOPS version. At Amazon right now the standard Vertex 3 is $270 shipped and the Max IOPS is $310 shipped. Of course the Max IOPS offers more than just better write endurance. It is also faster. So the real price difference due to the larger process size is probably less than $20. One also might want to look at the price points and margins Intel maintains on their CPUs for each tick cycle. Their price does not drop significantly each time they do another cost saving "tick" process shrink. The cost savings are not passed on to the consumer. Of course maybe we would see some of that savings if AMD could catch up with Intel and engage in another price war, but certainly the mere fact that the manufacturer saves money does not automatically result in a savings for the consumer.

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    Quote Originally Posted by gojirasan View Post
    The old write estimates for that process size were around 1500 p/e cycles, but of course neither company is going to be using those estimates. Instead the write endurance estimates are exactly the same as for 25nm cells. What that shows is not that these companies can get around the laws of physics, but that, without testing, they can claim anything they want which serves their marketing purposes.
    "Without testing"??? Certainly the flash memory manufacturers have extensively tested the endurance of their products. The large semiconductor manufacturers have extensive testing and reliability procedures for products both in development and production.

    There are flash memory spec sheets available from, for example, Micron. I haven't jumped through their hoops to sign up and be able to download their spec sheets on their flash memory, but if you are so concerned about this issue, I am surprised that you have not.

    As for your "estimates" of erase cycles, I'll take the spec sheet from a large flash manufacturer over your "estimates" every time. Semiconductor engineers are clever -- if they have to meet, say, 3000 erase cycles for a smaller process, they will usually find a way to do it. Process tweaks and optimizations, better equipment, testing and binning, etc.

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    C300 and M4 have same controller type. M4 is better for sequential ePeen while C300 is best for OS drive due to better random performance.

    There is no way that C300 with 34nm is less endurance than M4 with 25nm with same controller. If the two had different controllers than maybe possible etc. !

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    The point is this: the underlying technologies are making these shrinks more viable. It isnt always about the P/E, or just the 'endurance'. a controller that is smarter, and utilizes its NAND far better, more than makes up for it.
    Integrated ECC and other techs are also making your data more secure, with each and every generation.

    as i posted elsewhere on the forum, they arent going to make drives that last considerably shorter amounts of time, and then try to sell them to Enterprise users, or regular users for that matter.
    If they make these devices with small lifespans, no one will use them, thus making the billions and billions spent making the advancements, useless. a fools folly to invest these billions in R&D and then fabs, just to try to "trick" joe schmo, not to mention the multimillion/billion dollar corporations that use these devices, and have teams of guys with degrees researching every large purchase.
    They do all this so that some guys on a forum run some tests and finds out about the big "conspiracy" and blows the lid off of it? then they lose all that money? yeah right.

    it doesnt, and isnt going to, work that way. They arent that stupid.
    comparing MAXiops v V3 is not wise anyway, that is totally price gouged. Also, who is to say the endurance of the MAXiops IS really better>? does it have integrated ECC? is that controller designed and optimized for that nand? or is it just a marketing gimmick to sell some more drives?

    If I am buying a device with half the write capacity it should be half the price to give the same value.
    thats the point your missing my friend. it doesnt have half the write capacity. The P/E ratio is one factor amongst many that determine the drives endurance. You arent looking past P/E. Much like the saying "One cant see the woods, because the trees are in the way"


    What I expect this testing to show is that the traditional estimates based on process size are more or less wild-assed guesses
    quite the opposite. highly educated guesses that are probably set extremely low, simply to cover their ass.
    Last edited by Computurd; 06-20-2011 at 11:27 PM.
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  12. #462
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    I agree with Comp.

    With the new gen drives you are getting a better product for less cost.

    You are buying a product that performs faster & lasts longer. In addition data integrity is enhanced.

    The endurance test (so far) is demonstrating that new gen drives can write faster and incur less wear in the process. The 5 year warranty on the new gen (Intel) drives is also proof that Intel have more faith in the new gen drives.

    With regards to cost, don't forget that the 320 has power caps to reduce the risk of data corruption and other enhancements compared to older models, which add costs that offset the savings from NAND. Some of these costs/ measures are incurred due to the reduction in NAND die size, so there is a trade off, but overall you are getting a better product for less.

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    128tb. 34%.

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    Whatever you guys say, I still think that 34nm > 25nm in all aspects ( speed, endurance etc. ).

    It is really just physics. No amount of controller wizard magic is going to beat that !

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    Quote Originally Posted by bulanula View Post
    It is really just physics. No amount of controller wizard magic is going to beat that !
    Clever engineers have been demonstrating the absurdity of statements like that for decades.

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    erm...Bulanula... write endurance in this thread alone has been proving you wrong, the 25nm drive has been having fairly substantially higher writes per MWI percentage ( 34nm- 90.49TB @ 50%, 25nm- 97TB)
    and looking at intel spec sheets (I still havn't seen an official review on a 320 series 40GB drive),
    Writes- ~28% faster (45mb/s vs 35mb/s)
    reads- ~17% faster (200mb/s vs 170mb/s)
    4k IOPS read- ~20% faster ( 30k vs 25k IOPS)
    4k IOPS write- ~48% faster ( 3700 IOPS vs 2500 IOPS)
    on what is essentially the same controller
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    I did a full corruption test on my 320 today and I did not find any errors. The data read from every sector was exactly what I've written to it. I will be resuming the endurance test this evening.

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    As in pattern testing?
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    Quote Originally Posted by DragoonXX View Post
    on what is essentially the same controller
    Well I think everybody knows how Intel INTENTIONALLY throttled its controllers from the G1 -> G2 -> G3 so that is why the G3 has supposedly better speeds etc.
    so that the consumer would see an improvement. In fact, a G1 SSD with the unthrottled G3 firmware is essentially a 320 series ( not taking into consideration the 50nm of G1 vs 34nm of G2 and 25nm of 320 ) etc.
    However see that M4 is NOT throttled and slower than C300 in many random scenarios.

    25nm cannot physically be more endurant / faster than 34nm on the same controller with same firmware !

    It is like comparing a 2 litre engine and a 3 litre engine. In the same car with same weight etc. the 3litre will always be faster but if you put the 2litre in a lighter car ( better controller and firmware ) of course it will be faster than the 3litre one in a heavy car etc. !

    Show me an example of this proven wrong and I will get rid of all my doubts.

    In this thread we see that 320 > G2 because they are using supposedly different firmware and a different controller ?

    People just forget that nothing is infinitely scalable. Graphene cannot come soon enough.
    Last edited by bulanula; 06-21-2011 at 12:03 PM.

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    Quote Originally Posted by Anvil View Post
    As in pattern testing?
    Yes. I wrote the number of the LBA into each LBA and then read everything back to confirm it was 100% correct. I have hardware that can do this.

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    Quote Originally Posted by bulanula View Post
    Well I think everybody knows how Intel INTENTIONALLY throttled its controllers from the G1 -> G2 -> G3 so that is why the G3 has supposedly better speeds etc.
    Actually, most people do NOT know that, since it is absurd and untrue. The reason the speeds have increased are because of firmware improvements and flash memory improvements.

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    Quote Originally Posted by johnw View Post
    "Without testing"??? Certainly the flash memory manufacturers have extensively tested the endurance of their products. The large semiconductor manufacturers have extensive testing and reliability procedures for products both in development and production.
    This is not in dispute actually. I meant published testing. Not in-house testing that is treated like proprietary information. I have little doubt that they know the actual limits of their technology. Those numbers may not make it into their spec sheets however depending on whether the numbers put their products in a positive or negative light. They are in business to make money and can be expected to act in a way that is consistent with that. IOW, their data can be expected to have a strong bias in their favor at all times.


    There are flash memory spec sheets available from, for example, Micron. I haven't jumped through their hoops to sign up and be able to download their spec sheets on their flash memory, but if you are so concerned about this issue, I am surprised that you have not.
    Again, their numbers cannot necessarily be trusted to reflect real world experience or real world unbiased testing. However I will see if I can get my hands on some of those spec sheets.

    As for your "estimates" of erase cycles, I'll take the spec sheet from a large flash manufacturer over your "estimates" every time.
    My estimates? They are just the typical estimates that I have read from many sources over the years. Read any IEEE article on the subject and you will see similar numbers. They are just ballpark afaik however. Hence the usefulness of this testing.

    Semiconductor engineers are clever -- if they have to meet, say, 3000 erase cycles for a smaller process, they will usually find a way to do it. Process tweaks and optimizations, better equipment, testing and binning, etc.
    I have no doubt there are optimizations and tricks that might lead to improvements in write endurance, but what you are implying is an order of magnitude improvement. Those sorts of improvements do not come easily and generally require a fundamental breakthrough that would typically be trumpeted from rooftops. Not the proprietary advancements themselves of course, but some general idea of what they did. They might even apply for a patent.

    Write endurance in NAND flash is fundamentally limited by a breakdown in the thin silicon dioxide or oxide nitride oxide (ONO) dielectric layer(s) dividing the floating gate from the rest of the transistor (mainly the p-substrate). That breakdown is caused by the cycling electric fields used for program/erase. The process is not fully understood, despite having been studied for decades, but it may have something to do with electrons getting trapped in the SiO2 dielectric (trap-up) while quantum tunneling through it during application of program or erase voltages. Over time those electrons can form a conductive path through the dielectric. At least that's one theory of SILC (stress induced leakage current). The trapped electrons may also slow the tunneling current to the point that not enough charge gets transferred during the program or erase voltage application and Vt (threshold voltage) changes to the point that it represents a different binary state. Another theory states that positive charge gets trapped in the tunnel oxide when the silicon and oxygen from the SiO2 are separated. The oxide breakdown is accelerated by higher voltages and higher temperatures. As the transistors get significantly smaller with each process shrink the dielectric area for each transistor also gets smaller. You have the same electric field stresses over a smaller area. So the probability of the SiO2 going bad over time is greater on a per cell basis, despite the fact that when looked at over the entire array the probability is the same.

    Smaller transistors are also more sensitive to fluctuations in the number of electrons stored in the floating gate. With SLC cells this isn't so bad, but for MLC it makes things quite difficult, especially as the transistor ages and wears. With 2 bit MLC you have a low, intermediate-1, intermediate-2, and high voltage state that represents (binary) 00, 01, 10, and 11. As the process size gets smaller fewer and fewer electrons stored in the floating gate determine whether you are at, say, intermediate-1 or intermediate-2. This increases your BER (bit error rate) and requires more bits of EDC/ECC to correct it. This is of course similar to the problem that hard drives are having at the moment with their increasing areal densities. As areal density goes up, signal to noise ratio goes down and 512 bytes per sector is no longer enough to contain all the ECC bits they need to correct the increasingly frequent errors.

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    It seems you have a pessimistic view of semiconductor specifications. In reality, the large semiconductor companies are very careful in their released specifications. On most high volume parts, they have spent millions of dollars and thousands of man hours on reliaibility testing and qualification. Their industrial customers rely on the parts being able to meet the specs that are published. If a large semiconductor company claims the part will meet a certain spec, you can bank on it.

    No need to explain the physics of semiconductors to me. But you seem to have an ivory tower view of semiconductor manufacturing. People have been making similar claims about the limits of semiconductor processing for decades. And they have been continually proven wrong as clever process engineers and resourceful manufacturing equipment designers find ways to keep pushing the limits further out. As for patents, certainly many process patents are filed, but many important process techniques are kept as trade secrets, for various reasons.

    As for "order of magnitude", no, not if you mean a factor of 10, as that phrase usually means. When the 3Xnm flash first came out, 5000 erase cycles was not uncommon. With the 25nm flash from IMFT, I have heard both 3000 and 5000 erase cycles. So unless you are claiming that the physics dictate that the erase cycles from 34nm to 25nm must go from 5000 to 500, it is not an order of magnitude. Besides, the 3Xnm flash currently has numbers ranging from 3000 to more than 10,000. You know why? Process improvements and binning. The SSDs usually get the best chips from the wafer. The lower quality chips go to less demanding applications, like USB sticks and consumer electronics like cell phones or media players.
    Last edited by johnw; 06-21-2011 at 03:50 PM.

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    This increases your BER (bit error rate) and requires more bits of EDC/ECC to correct it.
    hence several approaches used in tandem to address the issue. integrated ECC on-die (ClearNAND) and raid "hybrids"/parity at the device level.
    as always, it is the underlying technologies that are being enhanced exponentially, allowing the effective use of these devices, and mitigating the very problems that you are listing.
    Stir in a bit of purposely low P/E ratios, set to very exacting standards, process improvements, and effective binning and you have WIN.

    there is a thread kicking around here that helped kick off some of this testing, and it concerns endurance, there are some listed specs from Intel endurance testing. those might be a bit enlightening to you, how low they set the bar for something to constitute a "failure"
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    Quote Originally Posted by Computurd View Post
    The point is this: the underlying technologies are making these shrinks more viable. It isnt always about the P/E, or just the 'endurance'. a controller that is smarter, and utilizes its NAND far better, more than makes up for it.
    Integrated ECC and other techs are also making your data more secure, with each and every generation
    Well I don't know if I agree with "more than makes up for it", but I agree that those things certainly can reduce the impact of a shrink if they are present. In any given case that can be a big if. Still, I don't see this as an excuse for producing an inferior product. Inferior to the one they could have made if they weren't so obsessed with saving a few dollars via a process shrink. Because, for the purpose of SSDs at least, that is all it is doing. Saving on manufacturing costs.


    as i posted elsewhere on the forum, they arent going to make drives that last considerably shorter amounts of time, and then try to sell them to Enterprise users, or regular users for that matter.
    If they make these devices with small lifespans, no one will use them, thus making the billions and billions spent making the advancements, useless. a fools folly to invest these billions in R&D and then fabs, just to try to "trick" joe schmo, not to mention the multimillion/billion dollar corporations that use these devices, and have teams of guys with degrees researching every large purchase.
    They do all this so that some guys on a forum run some tests and finds out about the big "conspiracy" and blows the lid off of it? then they lose all that money? yeah right.

    it doesnt, and isnt going to, work that way. They arent that stupid.
    comparing MAXiops v V3 is not wise anyway, that is totally price gouged. Also, who is to say the endurance of the MAXiops IS really better>? does it have integrated ECC? is that controller designed and optimized for that nand? or is it just a marketing gimmick to sell some more drives?
    Well "short" is relative. The ideal scenario for the industry as a whole is to have the products fail as soon after end of warranty as possible. You want repeat customers. Of course if their competitors are offering drives which last much longer and the public is aware of that fact they will have to increase the lifespan to compete. MLC drives are intended to be consumer devices. They are supposed to be for the average Joe who might take 10 years to write 80 TB.

    Even at 19nm an SLC device will have a long lifetime. So businesses would be expected to buy those. Keep in mind that at present the manufacturers aren't competing on write endurance at all, except for SLC sales to businesses. It just isn't a marketing point. Even when it could be as in the Max IOPS drive. My point isn't that these companies would intentionally design an SSD to fail post-warranty, but they certainly aren't going to go out of their way to stop it. When we do start seeing 2 bit and possibly even 3 bit 19nm SSDs in 2012 I think write endurance could be reduced to a point where, in 1-3 years, techies at least may start to notice something is very wrong. It wouldn't surprise me at all if the industry would like to subdivide the market more into long life SLC and shorter lived MLC drives.


    thats the point your missing my friend. it doesnt have half the write capacity. The P/E ratio is one factor amongst many that determine the drives endurance. You arent looking past P/E. Much like the saying "One cant see the woods, because the trees are in the way"
    I realize that p/e is just one factor in write endurance. It's just the only factor where the manufacturers seem to be moving backwards, not forwards. Even if they can manage to increase overall write endurance despite a process shrink, it still bothers me, because they are not producing as good a product as they could if they used more robust memory with larger floating gates. Whatever happened to "bigger is better"? I want my floating gate transistors to be super-sized! Also I didn't intend to say that a single process shrink has half the write capacity. I meant that *if* it does it had better be half the cost. It was an example. I could have used 30% as an example just as easily.


    quite the opposite. highly educated guesses that are probably set extremely low, simply to cover their ass.
    Highly educated wild-assed guesses are still wild-assed guesses, but I am also betting that they have been conservative with their p/e c. estimates in the past. That is what gives IMFT the overhead for their 3000 p/e c. 20nm flash and maybe their 5000 p/e c. 25nm flash. Although we will soon find out about that.

    As far as the Max IOPS goes, while it is difficult to be sure without the sort of testing going on here, I would be very surprised if it did not have better write endurance than the 25nm version. It is difficult to imagine how it could not. The larger floating gate can hold more electrons allowing for more fluctuations for a given voltage variation and the oxide layer can be larger too. It is an unusual case because it is a process size difference in the same controller generation so the write endurance and EDC/ECC etc must be assumed to be equal. And how could it be a marketing gimmick? I haven't noticed OCZ mention the theoretical write endurance difference at all. Although that is probably only because they would rather not even open that can of worms.

    Incidentally, it has occurred to me that the process shrinks are not all bad in theory if you take a long enough view. If they focus on making smaller sized chips, the OEMs could fit more chips on a given PCB resulting in greater interleave and higher speeds. Like going from certain 120 GB drives to 240 GB ones. It also means larger capacity drives. Although unless the price per GB drops dramatically they won't exactly be affordable. Also even if dropping a process size does halve the write endurance obviously doubling the capacity doubles the write endurance. but I don't think the limitations of floating gate NAND will scale enough for that. I think they will have to transition to something like 3D charge trap flash or even one of the emerging exotic non-volatile memory technologies.
    Last edited by gojirasan; 06-21-2011 at 04:58 PM.

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