AMD Zambezi news, info, fans !

[Ice009]

I simply expect 6/4 cores desktop BD (Zambezi) to be faster than 6 cores Thuban/4 cores Deneb @the same clock, ATLEAST on average. Anything else, then JF-AMD is a LIAR and Terrace/Savantu/Shintai/Any other Intel trolls were right on the money since the beginning.

That's a bit harsh to call JF-AMD a liar at this stage. Surely he knew what people are talking about when asking if IPC is higher.

btw good to see you here if you are the same guy from the Spurstalk message board.

[dess]

That is totally ok, BD's L1 is write through, i.e. writes to the L1 go directly to the L2, thus the L1 and L2 write performance should be more or less the same.

I don't think so, it would hold back execution way too much. There is a buffer here called coalescing cache, which seems to be disabled here.

To alleviate the write-through bandwidth requirements on the L2, each Bulldozer module includes a write coalescing cache (WCC), which is considered part of the L2. At present, AMD has not disclosed the size and associativity of the WCC, although it is probably quite small. Stores from both L1D caches go through the WCC, where they are buffered and coalesced. The purpose of the WCC is to reduce the number of writes to the L2 cache, by taking advantage of both spatial and temporal locality between stores. For example, a memcpy() routine might clear a cache line with four 128-bit stores, the WCC would coalesce these stores together and only write out once to the L2 cache.

http://www.realworldtech.com/page.cf...2610181333&p=9

[Opteron146]

I don't think so, it would hold back execution way too much. There is a buffer here called coalescing cache, which seems to be disabled here.
http://www.realworldtech.com/page.cf...2610181333&p=9

I know that article since David wrote it. The buffer is nice, but it is just a buffer not a part of L1. It just helps to bundle the data in bigger chunks thus some accesses to the L2 can be avoided, nevertheless, you write into the L2.
Or to quote David:

The purpose of the WCC is to reduce the number of writes to the L2 cache,

each Bulldozer module includes a write coalescing cache (WCC), which is considered part of the L2

[freeloader]

That's a bit harsh to call JF-AMD a liar at this stage. Surely he knew what people are talking about when asking if IPC is higher.

btw good to see you here if you are the same guy from the Spurstalk message board.

Plausible deniability on JF-s part. LOL

[gi0v3]

i'd like to ask something to those who actually put their hands on a real bd: in AIDA64, or Everest or whatever, the cpu is recognized as OctalCore, wih an "L"? 'cause i saw that in the screens from coolaler, and along with results and test methodology ( ddr3-1333, lawl) that OctalCore didn't sound right either... maybe it's just me and my poor understanding of how greek prefixes get transcribed in english, but if thuban is a hexa-core, bd should be octa, right?

[spursindonesia]

That's a bit harsh to call JF-AMD a liar at this stage. Surely he knew what people are talking about when asking if IPC is higher.

btw good to see you here if you are the same guy from the Spurstalk message board.

As far as i understand, i HAVEN'T called him a liar yet, because my previous comment is a conditional one. But perhaps i gave the wrong impression, i certainly don't think he is one now, things are not official, i don't consider those leaks legitimate.

BUT, i certainly want to hold him accountable for what he has informed us in the past, because out of that assurance, we have bash many supposedly Intel shills around here. I know i did, and if they actually come out right, i will feel kinda guilty, my self conscious can't justify that.

And YES, i'm spursindonesia from Spurstalk too, i've been a Spurs fan for quite sometime, since mid 90's era. So, which Kori's sheep are you ? I'm one of his old sheep, i know her since early 2000's when we were still in SpursReport forum, hehehe.

[Manicdan]

people are not banned for their opinion, they are banned for how they say it
no apology will be needed if somehow IPC is lower

[EniGmA1987]

Why cant we find someone who has a Interlagos and bench it at the same speed as a Mangy Cores. From there it should be simple math to find out the IPC difference. I know there are people on here with Mangy Cores, you mean to say NO ONE has an Interlagos? They are already launched and shipping so that means NDA is up on them. Why can we get numbers that way?

[undone]

you mean to say NO ONE has an Interlagos? They are already launched

No.

[jeanjean15]

Why cant we find someone who has a Interlagos and bench it at the same speed as a Mangy Cores. From there it should be simple math to find out the IPC difference. I know there are people on here with Mangy Cores, you mean to say NO ONE has an Interlagos? They are already launched and shipping so that means NDA is up on them. Why can we get numbers that way?

The date of the launch of the opteron interlagos is the 26 september so i suppose that it is still under NDA :

http://www.xbitlabs.com/news/cpu/dis...er_Report.html

[Mats]

Just search for OS6272WKTGGGU or OS6276WKTGGGU, they're listed in many places, but not in stock yet.

[rog]

Official launch date for the server part is Q4.

[dess]

I know that article since David wrote it.

Me too.

The buffer is nice, but it is just a buffer not a part of L1. It just helps to bundle the data in bigger chunks thus some accesses to the L2 can be avoided, nevertheless, you write into the L2.

I would think it is clocked much higher than the rest of the L2. The higher the L1 throughput is the less it holds back execution. So, L1 accesses needs to be as fast as reasonably possible. The ~22 GB/s of (apparent) L1 Write is roughly 1/6 only of the ~130 GB/s of L1 Read... So, you can store the results of a computation 1/6 the speed of reading your datas. True, the amount of initial datas are usually bigger than of the results, but the ratio is not always >= 1:6. There can even be more results than initial datas.

Of course, it all depends on the size of this WCC, as well, so that how often we running out of it. I hope it's reasonably sized. (The rather low number in AIDA64 could also come from that it writes 64KB [size of L1D], while the WCC is certainly lesser.)

[demonkevy666]

That is totally ok, BD's L1 is write through, i.e. writes to the L1 go directly to the L2, thus the L1 and L2 write performance should be more or less the same.
However, I wonder what is happening with the L2 read performance, for some strange reason it seems to depend on uncore clock:

2.0GHz: 11.9 GB/s
2.2GHz: 35.8 GB/s
2.4GHz: 12.5 GB/s
2.6GHz: 36.8 GB/s

That's a big difference ...

i think the the northbridge now has two P states.
i noticed there where p states modes in one of chew*'s post

[TESKATLIPOKA]

demonkevy666 Isn't NB affecting just the main memory? Maybe it affects L3 but I don't think L2 is at that speed, it should be at cpu frequency as was L2 in K10.

[flyck]

Me too.


I would think it is clocked much higher than the rest of the L2. The higher the L1 throughput is the less it holds back execution. So, L1 accesses needs to be as fast as reasonably possible. The ~22 GB/s of (apparent) L1 Write is roughly 1/6 only of the ~130 GB/s of L1 Read... So, you can store the results of a computation 1/6 the speed of reading your datas. True, the amount of initial datas are usually bigger than of the results, but the ratio is not always >= 1:6. There can even be more results than initial datas.

Of course, it all depends on the size of this WCC, as well, so that how often we running out of it. I hope it's reasonably sized. (The rather low number in AIDA64 could also come from that it writes 64KB [size of L1D], while the WCC is certainly lesser.)

It does have a buffer so they are not stuck by the write speed. And the l1 write is correct because you expect it to be in the facinity of the l2cache. However the l2cache speed is just incorrect (wether it is a hardware issue or an Aida64support issue). One would expect the l2cache to reach at least 50-80Gb/s (it should be a higher latency with higher bandwidth construction compared to the current x6 lineup.... but that one has a lower latency, a lower frequency with higher bandwidth.).

These results seem more like a read/write through up to the memory. So either a hardware or an Aida64 software issue.

[TESKATLIPOKA]

flyck If its a hardware issue and they can fix it then the performance should noticeably improve and it would explain the mediocre performance until now.

edit: on the Aida64 product page it says its fully optimized for BD so I would think its a hardware issue or maybe this is the throttled thing in bios chew* mentioned.

[-Boris-]

flyck If its a hardware issue and they can fix it then the performance should noticeably improve and it would explain the mediocre performance until now.

I personally hope BD is flawed. That means it could be fixed and everything will be better first half of next year. But if it's not flawed, and everything is right and it still sucks as much as rumors suggest, then even I may consider Intel.

[AsterixXx]

But if it is a hardware issue/problem then probably they need another stepping, aren't they? And that is more (too much) time for the final/retail revision, somewhere in december it could be out..oh man . I really hope that this cache problems can be fixed through software,bios etc.

[-Boris-]

But if it is a hardware issue/problem then probably they need another stepping, aren't they? And that is more (too much) time for the final/retail revision, somewhere in december it could be out..oh man . I really hope that this cache problems can be fixed through software,bios etc.

If it's some bigger problems, comparable to the TLB bug, then it will be fixed in Piledriver, and hardly before that.

[SBB]

Maybe the performance shown in the leaked benches (that are lower than what we would expect) is due to a bug, and fixing it is causing further delays?

[-Boris-]

Maybe the performance shown in the leaked benches (that are lower than what we would expect) is due to a bug, and fixing it is causing further delays?

But AMDs own benchmarks they showed behind closed doors hinted something wrong, they made GPU limited gaming benchmarks and in handpicked benchmarks they were only 20% faster than a unnamed i5 quad core, with an octa core! If even AMDs own benchmarks show lousy performance then it can’t be something that will be fixed until release, they wouldn’t bench on old defective chips from this spring. They would bench on the new release chips. They wouldn’t use defective BIOSes so that’s ruled out too.

[duron]

from a chinese site (zol)

Bulldozer summary of recent relevant information Part3 (9.20 update B2 stepping of the BUG)
http://translate.google.com.hk/trans...11_100864.html

Confirmed fraud lol

1) OBR all the results are released - this hands on a B0 stepping of the chip, and he measured success whether it is AMD K10.5, or Intel SNB / Nehalem there results in an anomalous situation. Furthermore, also admitted forging his own achievements.
2) AMD AM3 + slot will continue to be used for compatibility with the next generation of Bulldozer. http://diybbs.zol.com.cn/11/11_100645.html
3) DonanimHaber has released FX-8130P ES (B0) results. http://diybbs.zol.com.cn/10/11_99888.html

orig. chi
http://diybbs.zol.com.cn/11/11_100864.html

[flyck]

But AMDs own demo they showed behind closed doors hinted something wrong, they made GPU limited gaming benchmarks and in handpicked benchmarks they were only 20% faster than a unnamed i5 quad core, with an unnamed octa core at the same price! If even AMDs own demo show lousy performance then it can’t be something that will be fixed until release, they wouldn’t demo an old defective chips from this spring. They would bench on the new release chips. They wouldn’t use defective BIOSes so that’s ruled out too.

I corrected your post. The demo was to show they have a working product that is competitive not to show how it performs.

Who said is a bug or is defective? might as wel be deliberatly forgot an important setting thats affects performance. We really don't know, we do know the hardware is running though.. The leaks go from really bad to bad. All the leaks now indicate there is abolsutely no reason to bring out the FX8, let alone the FX6 and FX4 whom have no justice to exist at all according to these results. So yeah, wait before making a verdict is still in order. At this time we can only guess about the real performance. We can make our bets on the leaked performance of the samples and try to determine if there is something wrong or if it is going to be the same when they release.

[TESKATLIPOKA]

-Boris- what they tested was B2F and now we have B2G and who knows which Agesa code they had, because I saw the latest AGESA only with Asrock bios.

flyck nice correction