The fact you have continued to say that Digital PWM is in its infancy is incorrect and you have no idea about the CHiL setup (all new design) that ASUS is utilizing on their P67 boards. You claim you did research and read papers, well that is about the same as me claiming to be a heart surgeon because I read medical documents on becoming a heart surgeon.
You also hinted that UEFI might not be as stable as a BIOS design. This is just FUD as I can tell you for a fact that this is not true and just another marketing point from Gigbayte as they were unable to get UEFI on their boards due to engineering problems. They will move to UEFI shortly and also to a Digital PWM, so it will be interesting to see what messaging you provide from Gigabyte next quarter.
As a hint to the marketing BS in your post I leave you with these three nuggets to answer truthfully until launch when we can really discuss their 24-phase power system and just how it actually operates or you can actually read the Intersil documentation and then comment on the multiplexing aspects of the design and what that truly means in transient response among other things.
1. Why does Gigabyte default the Bclk to a non-standard 99.80MHz?
2. Sandy Bridge has a digital SVID design now, what is required by an analog setup to properly handle CPUVID?
3. What is the maximum TDC output of Sandy Bridge at the allowable cpu core voltage limit of 2.0V?