AMD to Start Production of Desktop "Bulldozer" Microprocessors in April.

[Florinmocanu]

lots of cache... sigh... doesnt sound very promising...
whenever somebody put lots of cache on a chip in the past it was done to boost performance when tweaking the core wasnt possible or too much of a hassle...
this is THE new architecture and it comes with lots of cache instead of using as much die space for logic as possible... idk, to me this sounds like bad news...
then again, this is a server part anyways and not aimed at desktops, so i guess there lots of cores with lots of cache is good news and fp perf and ipc doesnt matter than much... i guess itll do well for servers... doesnt sound like itll do well in the desktop area at all though :/

not true, some of the most powerful CPUs in the world have tons of cache (some IBM machines have crazy specs, but ofc, they are not x86 cpus), much more than 16 MB so that they can load huge chunks of data straight into the cpu. It's good to have lots of cache, if you can put it to good use.

I was actually thinking, cache need will increase in the future, because as the cpu gets faster, more data is being processed so big amounts of cache will be required.

16 MB of cache for 8 cores doesn't sound bad, I7s and Phenoms have 8-9 MB of total cache for 4 cores or 6, 16 MB for 8 looks just like a normal evolution to me.

it's 1MB of L2 for each core, 2MB per module and an extra of 8MB L3 shared among 8 cores, 1MB per core, which doesn't seem that much. I7 quads have 6 MB L3 for 4 cores, 1.5 MB per core, higher ratio than what bulldozer will have.

[JF-AMD]

Wondering if that is due the current performance

Policy is not to release benchmarks before launch.

[JF-AMD]

That's a real surprise from AMD...

Originally thought that Llano will launch in Q2, and Bulldozer in Q3 / Q4.

Talk to me next week about this.

[JF-AMD]

Just a question Why april ?
Why not it's not starting just after first sample yet ?

I know APM is good, but yield need most time around 6 months before going good. 4+6=10 so november 2011 ???? Why it's sayed end of Q2 and start of Q3 meaning june/july on xbitlabs ?

my guess was already end of june, but i was thinking bulldozer was starting in january.

I just hope evrything will be good for BD samples, i would like a new fail from AMD, they don't need it, and i don't need wait so more for buy a new CPU

Why are you assuming that the article is correct. Remember when I said wait until next week? As I have said before, unless you are really in this industry (and, specifically at AMD) it would be hard for you to predict the actual schedules.

[JF-AMD]

lots of cache... sigh... doesnt sound very promising...
whenever somebody put lots of cache on a chip in the past it was done to boost performance when tweaking the core wasnt possible or too much of a hassle...
this is THE new architecture and it comes with lots of cache instead of using as much die space for logic as possible... idk, to me this sounds like bad news...
then again, this is a server part anyways and not aimed at desktops, so i guess there lots of cores with lots of cache is good news and fp perf and ipc doesnt matter than much... i guess itll do well for servers... doesnt sound like itll do well in the desktop area at all though :/

I don't understand you guys. Intel has big caches and everyone complains that AMD's caches are too small. Then, if you think AMD has big caches you turn that into a negative.

[xdan]

This masive L2&L3 cache it would be a fail if it is as slow or just a litte better than Phenom II/Thuban cache.
Let's not forget that Thuban L2 cache is 30-60% slower, and L3 cache is even 2-3 times slower than Lynnfield's cache...
And SB cache is faster than Lynnfied , not to count SB EX or Ivy Bridge on 22nm.
The best favorabile situation for Amd is that Bulldozer to be equal to SB.
i5 760...


Thuban

[JF-AMD]

Obsessing about the specs of individual pieces of an architecture without understanding the whole thing is really not going to get people any closer to understanding the whole thing.

Total performance per socket will be the yardstick to measure everything on. Short of that, everything is just idle speculation.

[saaya]

I don't understand you guys. Intel has big caches and everyone complains that AMD's caches are too small. Then, if you think AMD has big caches you turn that into a negative.

who complaints that amd caches are too small?
first time ive heard this... people complain that amd has a notably lower ipc than intel...

im just saying, historically from what ive seen, new archs use cache more efficiently and focus on that, efficiency, and big caches were always a plan B to boost an existing architecture to refresh it later... to see a new arch launch with large caches seems odd to me... then again k8 launched with 2x the cache of K7...

[Tomasis]

who complaints that amd caches are too small?
first time ive heard this... people complain that amd has a notably lower ipc than intel...

im just saying, historically from what ive seen, new archs use cache more efficiently and focus on that, efficiency, and big caches were always a plan B to boost an existing architecture to refresh it later... to see a new arch launch with large caches seems odd to me... then again k8 launched with 2x the cache of K7...

according to your logic, i7 must suck at big time

[FlanK3r]

this are only speculations...from only size cache u can say nothing.

[informal]

I'll trust JF-AMD when he says we should wait Analyst Day.
As for the big caches and IPC comments,commenting on how fast or slow is BD in each of these categories is futile since it's all speculation until launch.We like speculating,but saying that somehow big cache is now suddenly a bad thing is double standard in my book(since the naysayers disregard the fact intel will be doing the same thing with their 8 core SB chips,adding massive L3).

[Mats]

The first Conroe from 2006 had 2 MB L2 cache per core.

The first Bloomfield from 2008 had 2 MB L3 cache per core.

The first Sandy Bridge will have 2 MB L3 cache per core.

What's your problem.

[blindbox]

The first Conroe from 2006 had 2 MB L2 cache per core.

The first Bloomfield from 2008 had 2 MB L3 cache per core.

The first Sandy Bridge will have 2 MB L3 cache per core.

What's your problem.

L3 can be shared though.

I don't see a problem with what he said. Thuban had constant L3 amount compared to Deneb.

[Olivon]

Policy is not to release benchmarks before launch.

So why we got SB Anandtech preview ?

[Mats]

L3 can be shared though.

What's with your attitude? We're talking about cache size, only.

[Mats]

So why we got SB Anandtech preview ?

Maybe SB isn't made by AMD? Just guessing.

[Olivon]

Maybe SB isn't made by AMD? Just guessing.

Intel do it, why not AMD ?

[Mats]

Intel do it, why not AMD ?

It must be because they have different policies.
Also, I think AMD have more to loose if they give away any performance specs half a year before launch.

I know I wouldn't.

[JF-AMD]

Intel do it, why not AMD ?

I can think of a lot of things that they do/did that we do not.

Just because someone else does it doesn't mean it's right.

[Dimitriman]

who complaints that amd caches are too small?
first time ive heard this... people complain that amd has a notably lower ipc than intel...

im just saying, historically from what ive seen, new archs use cache more efficiently and focus on that, efficiency, and big caches were always a plan B to boost an existing architecture to refresh it later... to see a new arch launch with large caches seems odd to me... then again k8 launched with 2x the cache of K7...

historically, intel has always had more and has always depended more on cache than amd.

[ajaidev]

So why we got SB Anandtech preview ?

As far as i know it was not approved by Intel, this is what i have said befour also.

The other possibility is that someone high up gave the order because there was NO talk's about it anywhere in the R&D center where i was and even if it was a marketing thing still we would have gotten some clue before the review was up.

Intel's policy as far as i know it is "No CPU info before launch, No sensitive info after launch, No sample microcode sharing, No added info to reviewers, No codename expose"

It is still possible someone high up gave a order and made it all possible but i am quite sure that marketing team was not involved. As a point of rule all Intel's R&D talk with each other all the time and in real time.

[Olivon]

I can think of a lot of things that they do/did that we do not.

Just because someone else does it doesn't mean it's right.

I understand John

But, as a consumer who has to change his rig soon, what arguments will make me wait for Bulldozer ?

[blindbox]

What's with your attitude? We're talking about cache size, only.

And you decided so that we calculate cache size per core instead of total cache size. What's up with my attitude?

[xdan]

Intel do it, why not AMD ?

It must be because they have different policies.
Also, I think AMD have more to loose if they give away any performance specs half a year before launch.

I know I wouldn't.

I understand John

But, as a consumer who has to change his rig soon, what arguments will make me wait for Bulldozer ?

+1
If Bulldozer it's really a "wonder" Amd should make a preview of performance on 15 january at SB lauch....If Bulldozer it's better than SB than Intel sales will be hurt , people will wait for Bulldozer or for Intel price cuts.
But if Amd will show nothing in january-february than Intel will continue to gain market share, and Amd i expect to have 1-2 quarter's very negatives because i expect i3's SB to be equal to an actual Phenom II X4, and i5's if they start at 179$ they will kill X6's.
The launch of Bulldozer is probably in june or july i expect...

[Florinmocanu]

Blindbox, he was just showing that intel CPUs have a higher ratio of L3 cache per core than BD. It just shows that the general trend is to go high with cache since it helps a lot streamline the work, no useless waiting.