AMD's Bobcat and Bulldozer

[FlanK3r]

JF: its possilbe at AM3+ (under heatspreader) get 5-6 modules Zambezi? For future models or if it will needed ?

[JF-AMD]

Can't comment on that because a.) it is client and b.) it is future product plans.

[Sn0wm@n]

For 8 core CPU 754 pins.
Dual PCIe controller 188 pins.
Quad channel memory 374 pins
Total: 1306 pins

For 16 core CPU 1508 pins.
Dual PCIe controller 188 pins.
Quad channel memory 374 pins
Total: 2070 pins

So it looks like AMD has been stuck on 754 pins for a long time too.

please tell me you know what your talking about ..... because your assumption seems like some wild guess and nothing else

[stangracin3]

For 8 core CPU 754 pins.
Dual PCIe controller 188 pins.
Quad channel memory 374 pins
Total: 1306 pins

For 16 core CPU 1508 pins.
Dual PCIe controller 188 pins.
Quad channel memory 374 pins
Total: 2070 pins

So it looks like AMD has been stuck on 754 pins for a long time too.

you fail at writing down numbers
188+374+754=1316

which means 1306+754 is not equual to 2070
1316+754=2070

[generics_user]

AMD will not have a 2P client board.

http://bit.ly/chNf9B

There is no market size that will justify it.

amd never had client boards


i still hope for asus or EVGA to put out an overclockable dual socket board

[Wade]

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)


Regards, Hans

and he was right the whole time.

[danielkza]

and he was right the whole time.

For the wrong reasons though. We'll only found out what actually went wrong in the next weeks.

[radaja]

i doubt we'll find anything out from AMD,maybe others but not them

[Hornet331]

First time in 3 years it has more viewers then the intel section.

[Manicdan]

First time in 3 years it has more viewers then the intel section.

it happened when llano came out, and when bobcat came out
the few days before and after any launch, a section becomes much more popular. when fermi launched i think people saw >1000 users in the news section for a day

[nn_step]

For the wrong reasons though. We'll only found out what actually went wrong in the next weeks.

Well the L1 and L2 latencies look like a good starting point.
Then looking at the decode stage, it seems like a bad design to share anything past the Microcode.
The ALUs seem to be starving if you ask me.

[Dresdenboy]

and he was right the whole time.

I think not. But it still remains to be seen

Who said that engineers (who provided the data for the slides and talked about constant IPC in their papers) had to develop an architecture which optimally runs code for AMD's family 10h or Intel's Sandy Bridge? It's similar to the APUs: with legacy code they are OK, but to shine they need new code. Or did nobody wonder why AMD startet to talk that much about software in the past years?

So if with appropriately compiled code BD it isn't able to achieve that "constant IPC" claim, then it failed.

In my next article I'll show how extremely legacy code like SuperPi is simply limited by a decode rate of 1-2 instructions/clock. Remember: there are actually 4 decoders.

[Dresdenboy]

Well the L1 and L2 latencies look like a good starting point.
Then looking at the decode stage, it seems like a bad design to share anything past the Microcode.
The ALUs seem to be starving if you ask me.

The L1 latency seems to be well hidden, if you look at my instruction execution analysis, where many memory ops are included:
http://translate.google.com/translat...#content_start

It also has a way prediction which should be able to reduce latency in some cases. But still it's and out of order design and having only 2 EX units it should be easy to fill the voids.

I also find the decode stage to be a problem, but not because of being shared (this only causes a significant influence if it has to decode inefficiently ordered code).

[undone]

I start to smell some 'optimization bias' changes between win amd intel.

[Dresdenboy]

I start to smell some 'optimization bias' changes between win amd intel.

This improvement is just the result of the OS scheduling threads belonging together on the same module and not some random module. It has nothing to do with code optimization (which is often biased, but then there can be 2 or more code paths).

[Borden]

Now I'm worried about Trinity, but at least it will use 2 Piledriver module and no BD

[AliG]

Bumping this thread to give a shout out to Terrace215.

Dude called BD's IPC decreasing months before it happened, and it only took AMD 6 years to finally Ryze back to the top

[drmrlordx]

This post is so old it still has JF-AMD in it . . .

[AliG]

This post is so old it still has JF-AMD in it . . .

LOL right?

Still, I felt Terrace215 was due some credit for his innovative Bulldozer IPC Decrease Algorithm. Poor guy was right from the start but chased out of the forum by everyone who thought the notion of AMD going backwards in performance was ridiculous.

[StAndrew]

LOL right?

Still, I felt Terrace215 was due some credit for his innovative Bulldozer IPC Decrease Algorithm. Poor guy was right from the start but chased out of the forum by everyone who thought the notion of AMD going backwards in performance was ridiculous.

But he was right for all the wrong reasons. He was right by accident.

[AliG]

But he was right for all the wrong reasons. He was right by accident.

Was he? I recall him being a bit of a , but basing it off the fact BD modules had 2 really weak integer units with 2 ALUs each (as opposed to Intel's 4 shared ALUs with SMT) and the lack of positive leaks that late into launch.

[StAndrew]

Was he? I recall him being a bit of a , but basing it off the fact BD modules had 2 really weak integer units with 2 ALUs each (as opposed to Intel's 4 shared ALUs with SMT) and the lack of positive leaks that late into launch.

Maybe; he didn't come off as too intelligent; maybe he just had trouble with effective communication? A lot of it was just conjecture and he got lucky from what I recall... I still blame Han's.

[vario]

Yea, after i went FX2 (vishera) , i did some comparisons max clock vs max clock using stable settings and same air coller.
It was not a clear cut win for the vishera ...
I remember even some discussions after i did it and people generally didnt like the idea ;-) .
Of course ON THE WHOLE vishera was better than the X6, but pretty much just because of newer process and some things like AES and other new instruction sets.

Oh i even have them.
FX 8320 @4424Mhz 1.46v NB@2520Mhz 1.32v RAM 1966Mhz 9-9-9-27-46
X6 1055T@4100Mhz 1.50v NB@2929Mhz 1.30v RAM 1562Mhz 7-8-8-23-27

3Dmark 13 Default FX=Ice Storm 114078 G190964 P47352
X6=Ice Storm 122668 G199771 P52181
FX=Cloud Gate 16731 G30975 P6412
X6=Cloud Gate 15565 G30841 P5694
FX=Fire Strike 3778 G3995 P8658 C1678
X6=Fire Strike 3674 G3821 P8774 C1701

Cinebench 11.5 64bit FX=OpenGL 76.19 CPU 7.62 SC=1.17
X6=OpenGL 73.25 CPU 7.22 SC=1.23

I did more tests, but FX only really was substantially faster in video transcode.
Makes you wonder where they would be if they would do Liano x8 +l3 instead of BD.

[chew*]

4075.7......Oldscarface........15.59.688..15.5x263 .....877mhz.....6-5-6-18....3/10..790FX

Deneb was faster cpc than thuban if you recall.

http://chew.ln2cooling.com/?Qwd=./Ll...competitor.jpg

It certainly would have offered improvements. I think the R&D would have been costly for the gains, there were other complications.

[AliG]

I think Chew mentioned there was internal discussion about building off Llano instead but they had some confidential reason it couldn't be done.

Thuban was actually pretty good value. It wasn't quite as good as the Intel offerings, but they clocked well and had reasonable IPC. Bulldozer flat out got steamrolled; if nothing else, all the delays gave Intel time to launch Sandy Bridge first.

Edit:
Chew beat me to it, guess it had to do with yield.