AMD's Bobcat and Bulldozer

[Dimitriman]

Not in a case when terrace is a shareholder in certain company . IF BD fails(it will not,but for a sake of an argument) the stock in that company raises and he profits.Simple math

You speak the truth therrr

[Sn0wm@n]

See, that statement is what gets people in trouble. Someone reads that statement and assumes 10% lower performance.

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

megaquote FTW!!!!

[Tomasis]

That's a module mate. 1 core in that module has higher IPC than a Thuban core. Pretty simple. But, when both cores in 1 module work on 2 threads, than you loose 10% performance per core because of the shared components. In single thread scenarios, 1 of the 2 cores works at 100%.

veryyy simple explanation

[JF-AMD]

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

Some people like to do math but they don't like to do all the math.

[BatteryOperated]

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

Some people like to do math but they don't like to do all the math.

megaquote!!!

[Manicdan]

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

Some people like to do math but they don't like to do all the math.

best math since 2+2=4

[terrace215]

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Because that is what Alsup is saying is NOT the case. (integer performance, yes, but integer performance/clock drops slightly in a thread, made up for by a faster clock)

Anything less than that statement could be satisfied through the not-in-dispute FP improvements, or the more cores part. It's got to be: Integer (not FP), IPC (or "performance/clock", not just "performance"), Single-threaded

Something like, "BD will have higher single-threaded integer performance/clock than the previous generation."

That would actually address (and contradict) the statement that Alsup made.

[cegras]

Aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaargh

I'm devolving from the level of discussion in this threaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaargh

[blindbox]

I'm breaking into tears.

Well I for one likes to keep on topic.
madcho, the 33% more cores for 50% more perf is on server loads. You can't reliably guesstimate from there.

[geo]

Here is what it means.

Bulldozer cores are like Intel Hyper-threading cores.

The primary difference is that AMD throws more transistors at the problem by giving each thread it's own set of integer execution units. Added to the fact that AMD’s distributed schedulers and instruction grouping. This is a clear architectural trade-off of performance and decreased control complexity versus size and increased execution complexity. Replicating two full featured ALUs uses more die area, but provides higher performance for certain corner cases, and enables a simpler design for the ROB and schedulers.

The honest truth is if NO CPU designed yet, can keep a constant throughput of 2 instructions per clock. So the more efficient design of the Integer cores, suggest that we shouldn't expect any performance drop at all. [For 99.9% of all user applications ]

ok. if there are no single thread perf drops, then going by the article that compares Real Cores vs HT there should be atleast 40 % improvement compared to similarly clocked Phenom2 at same clocks!! ?

[terrace215]

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

What happened to power in those statements? Does performance per watt suddenly not matter?

Or could it be that the adding most of a second integer core actually uses a nice chunk of power when adding that 80% performance?

Is it possible that the thing to look at would be the performance/W improvements that the 2 different degrees of resource-sharing provide? Nahhhhhh.

[terrace215]

How many times do I have to tell you that bulldozer has higher IPC than our current architecture?

Is somebody being paid by intel to continually post these statements?

That statement is from AMD's ex Chief Architect. I think the guy is now retired, but if you think Intel is paying him to post on comp.arch...

And your previous statements manage to artfully avoid getting all of "integer" "IPC" (note, IPC, not "performace") and "single-threaded" covered.

It wouldn't be hard to state, assuming your new architect will sign off on it.

[Sn0wm@n]

Can you say, "single-threaded integer IPC will be higher than the previous generation" ? .

read my previous megaquote ....YES it will be improved ....

[Hornet331]

Come one this gets boring... we can discuss the matter when we have actuall numbers. As it stands now BD is expected to increase IPC and ST performance. Theres not much point in it discussing with a marketing guy and try to make him slip some information regarding this concern.

[blindbox]

read my previous megaquote ....YES it will be improved ....

Apparently he wants it to be very specific. He thinks something like, AMD drops integer performance to 10% of K10, but increased FP performance by 1001%, hence increased single-threaded performance.

Meh, looks like he still haven't read the whole thread. And he's running out of things to argue about.

EDIT: Anyway, third question answers terrace215's power questions. Honestly man, read the thread, read the slides, we're not here to spoonfeed you, especially seeing how eager you are. Stop nitpicking, and don't say you're not nitpicking.

http://blogs.amd.com/work/2010/08/30...%80%93-part-2/

Nothing that we don't know of though.

[Jowy Atreides]

That statement is from AMD's ex Chief Architect.

See:

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

Ex architect is EX for a reason. His version of bulldozer sucked and was cancelled until it could be satisfactory.

[LightSpeed]

^^

lol

@ terrace215: Give it a break man?

[generics_user]

i think that a certain forum rule REALLY describes what certain persons are doing in here...


19. Trolling
Anyone entering the forum with the express intent to cause trouble or harm is subject to immediate and permanent ban.

[Shadov]

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Because that is what Alsup is saying is NOT the case. (integer performance, yes, but integer performance/clock drops slightly in a thread, made up for by a faster clock)

Anything less than that statement could be satisfied through the not-in-dispute FP improvements, or the more cores part. It's got to be: Integer (not FP), IPC (or "performance/clock", not just "performance"), Single-threaded

Something like, "BD will have higher single-threaded integer performance/clock than the previous generation."

That would actually address (and contradict) the statement that Alsup made.

Terrace are you buying a ready product or 1 kg of Ghz like tomatoes?

Who cares about clock for clock if the part performs better in a given TDP budget which it was designed for.

To everyone else reading this thread: can we start a pool for Movieman to ban terrace from all threads including the word AMD?

[Solus Corvus]

I wouldn't be surprised for this to hold true core for core at the same frequency.

I won't discount the possibility that taking out extra ALUs could lead to a bottleneck. We don't know enough to say otherwise at this point.

But I'm not going to reject the possibility that with all the frontend and cache improvements 2 well fed ALUs could beat 3 poorly fed ones. ALU count alone doesn't determine the average IPC, only the max. K10 isn't anywhere near 2 on average as you pointed out.

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Why all the fascination with integer instructions? Real code uses a mix of int, fp, logical, and memory instructions. If the IPC of BD versus K10 increases when executing real world code isn't that what matters?

What happened to power in those statements? Does performance per watt suddenly not matter?

Or could it be that the adding most of a second integer core actually uses a nice chunk of power when adding that 80% performance?

Is it possible that the thing to look at would be the performance/W improvements that the 2 different degrees of resource-sharing provide? Nahhhhhh.

Of course adding a whole second set of execution resources is going to increase power consumption compared to HT. It's also going to perform better.

[flippin_waffles]

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Because that is what Alsup is saying is NOT the case. (integer performance, yes, but integer performance/clock drops slightly in a thread, made up for by a faster clock)

Anything less than that statement could be satisfied through the not-in-dispute FP improvements, or the more cores part. It's got to be: Integer (not FP), IPC (or "performance/clock", not just "performance"), Single-threaded

Something like, "BD will have higher single-threaded integer performance/clock than the previous generation."

That would actually address (and contradict) the statement that Alsup made.

What difference does it make, either way? I'm starting to wonder if you and your buddies are'nt just sitting around your mothers basement drinking pop, laughing at all the sh1t you're stirring up in various AMD threads.

[Sn0wm@n]

its obvious that he his scared that bulldozer will become the 2010 pentium killer ... so his stock will likely plunge ... poor him

[generics_user]

Terrace are you buying a ready product or 1 kg of Ghz like tomatoes?

Who cares about clock for clock if the part performs better in a given TDP budget which it was designed for.

To everyone else reading this thread: can we start a pool for Movieman to ban terrace from all threads including the word AMD?

i guess that it's up to the admins to decide on this issue; not on us to start a witchhunt on certain persons....

while i think that the only purpose of terrace' posts is to create chaos and troll 80% of all forum members (and to secretly earn some more money from his shares / or directly from intel) we aren't the ones who should decide if a user gets banned only because he says things that we don't like

[terrace215]

read my previous megaquote ....YES it will be improved ....

You guys apparently don't realize that:

performance != performance/clock (IPC)

IPC != single-threaded IPC

and that the Alsup statement was about the *Integer* pipeline.


It doesn't matter how big the font is that says "Single-thread performance is higher." or "Bulldozer IPC will be higher." Neither of those address the Alsup claim which was that:

Single-threaded integer performance PER CLOCK (i.e. IPC) will be ~5% lower.

I would not have thought that the distinction would require a great deal of analytical reasoning ability to comprehend, but the numerous replies (with one exception that I've seen) indicate that I am either incorrect in my assessment or that educational systems are failing.

And really, all the personal stuff because someone posts something you disagree with? Really?

[Solus Corvus]

IPC != single-threaded IPC

It doesn't?