AMD's Bobcat and Bulldozer

[blindbox]

terrace215 totally has never read any of JF-AMD's posts. JF-AMD has said COUNTLESS times that IPC will be HIGHER than K10.

richierich:
I think Movieman is just too scared to open this thread . Moderator's horror.


It's a problem when you're denying some things when facts are IN YOUR FACE. -5% IPC compared to Thuban? Wow where did that 33% more cores yet 50% more perf compared to magny core on server loads arguments went to? Or Dresdenboy's analysis of the uarch which are at least better than listening to some ex-chip architect who hasn't worked on the processor (of course, I mean BD) for 3 years? Or that none of you guys even mentioned about the improvements in other areas, and keeps attacking the fact that AMD removed something. Well, they added stuff as well. Heck, even the fact that the design is a ground-up design should mean something.

What Sunfire said anyway. You guys need to read the thread from the start.

[BatteryOperated]

Huh ? K10 has 3 ALUs and 3 AGUs, BD has 2+2. Contrary to what informal&co were hipping around, BD's integer cores are simpler and less powerful than on K10. Which is no surprise, something had to give in order to keep a module size under control.

All the improvements done together with the frequency increase are meant to compensate the 3rd unit. You have the information in the AMD slide ( ...without significant loss on the serial single-threaded workloads components ), you also have the comments of M. Alsup ( ...and
loose a little architectural figure (5%-ish) of merit due to the
microarchitecture ). It all fits together now, irrespective of what marketing is trying to portray.

Without significant loss = loose (5%-ish )

AMD is giving up single threaded performance and is focusing on through-output. They've realize it is pointless to try and compete with Intel on "fat" cores ( already in commercial benchmarks they need a 2-to-1 ratio to stay competitive with Xeons ) so the alternative path they are taking is to cram as many cores as possible in a given die size and clock those simple cores as high as possible.

Magny Cours isn't adequate for this since the core size is still too big and the core advantage over Xeons at the same process node is too small. With MC, AMD had a 50% advantage in the number of cores. With BD they will have 60% ( and much higher frequency ) over same timeframe Xeon and this will only increase in the future.

Hmmmm... do you think not being caught in lie is the same as telling the truth?

[Sn0wm@n]

savantu is starting to post more .. and we get less terrace .... we get more terrace if savantu post less ... anyone has a theory as to why ???

<totally rhetorical question, NOT real numbers>
Which would you rather have:
80% of the performance with 50% of the cost and 50% of the power consumption
100% of the performance with 120% of the cost and 120% of the power consumption
</end rhetorical question>

People keep seeing that 80% number and thinking that it is a compromise. What they don't understand is that by sharing components we are able to add more cores in the same die space and same power budget.

It is by no means 80% of today's performance.

good to know

so to terrace and savantu ... i think its clear that BD will be more powerfull than K10.5

[-Boris-]

Huh ? K10 has 3 ALUs and 3 AGUs, BD has 2+2. Contrary to what informal&co were hipping around, BD's integer cores are simpler and less powerful than on K10. Which is no surprise, something had to give in order to keep a module size under control.

All the improvements done together with the frequency increase are meant to compensate the 3rd unit. You have the information in the AMD slide ( ...without significant loss on the serial single-threaded workloads components ), you also have the comments of M. Alsup ( ...and
loose a little architectural figure (5%-ish) of merit due to the
microarchitecture ). It all fits together now, irrespective of what marketing is trying to portray.

Without significant loss = loose (5%-ish )

AMD is giving up single threaded performance and is focusing on through-output. They've realize it is pointless to try and compete with Intel on "fat" cores ( already in commercial benchmarks they need a 2-to-1 ratio to stay competitive with Xeons ) so the alternative path they are taking is to cram as many cores as possible in a given die size and clock those simple cores as high as possible.

Magny Cours isn't adequate for this since the core size is still too big and the core advantage over Xeons at the same process node is too small. With MC, AMD had a 50% advantage in the number of cores. With BD they will have 60% ( and much higher frequency ) over same timeframe Xeon and this will only increase in the future.

3 ALU/AGUs is less than 2 ALU + 2 AGU. Each BD core is stronger than Phenom II at that point.
Bulldozer as a whole will be faster, both per core and per socket, 50% increase with 33% more cores would be impossible if it wasn't.
"Only" 80% increase from second core is the exact same thing as saying 11% faster per thread when only one core is utilized. That means faster at single threads.

Most of the facts we have doesn't fit your theory. The only thing you have - still - is the quote from Mitch Alsup here: http://groups.google.de/group/comp.a...14f6049?hl=de#

And it seems to me that you haven't read all that he has to say.

[madcho]

I've made some calc about BD, it's my own calc so it's pure speculation, nothing real, but it's awesome.

i used Magny cour 2.2ghz 12 cores for base and used the +50% +33% more core, i used 7.95x speed up for cinebench 11.5 for 2P 2x6 cores opterons.

And used the 80% from AMD slide to calc the multithread speed up of BD.

So if my calc are not f*cked ( i hope so ), i get :

16 cores ( 2x8 on G34 or 2*4 modules ) with 8.48x multithread speed up.

I set the IPC to magny cour to 1. So P1 ( P in single thread ) is 2200*1=2200, and P2 ( P in multithread ) is 2200*1*7.95=17.490k

+50% perf for BD in multithread it's said.

so : 17.490*1.5 = 26.235k.

So P1 for BD is 26.235k/8.48=3093.75.

So P1 BD / P1 magny cour = performance improvement for BD = 3093.75/2200=1.40.

So we know P = F * IPC, and we the deeper pipeline target 20 to 25% frequency improvement.

With 20% we get 2640mhz, so i use 2.6ghz for more rationnal number.

Aproximation IPC is P/F=3093.63/2600=1.189 to compare to 1 taked for magny cour.

SO I GUESS I'M CRAZY TO DO SOME STUPID CALCS LIKE THAT BUT I DON'T WANT GO TO ASYLUM ... TY

[informal]

terrace and savantu are speaking about mystical losses in IPC,so they must have BD chips in their hands,right?Right.

[JF-AMD]

Huh ? K10 has 3 ALUs and 3 AGUs, BD has 2+2. Contrary to what informal&co were hipping around, BD's integer cores are simpler and less powerful than on K10. Which is no surprise, something had to give in order to keep a module size under control.

All the improvements done together with the frequency increase are meant to compensate the 3rd unit. You have the information in the AMD slide ( ...without significant loss on the serial single-threaded workloads components ), you also have the comments of M. Alsup ( ...and
loose a little architectural figure (5%-ish) of merit due to the
microarchitecture ). It all fits together now, irrespective of what marketing is trying to portray.

Without significant loss = loose (5%-ish )

AMD is giving up single threaded performance and is focusing on through-output. They've realize it is pointless to try and compete with Intel on "fat" cores ( already in commercial benchmarks they need a 2-to-1 ratio to stay competitive with Xeons ) so the alternative path they are taking is to cram as many cores as possible in a given die size and clock those simple cores as high as possible.

Magny Cours isn't adequate for this since the core size is still too big and the core advantage over Xeons at the same process node is too small. With MC, AMD had a 50% advantage in the number of cores. With BD they will have 60% ( and much higher frequency ) over same timeframe Xeon and this will only increase in the future.

How many times do I have to tell you that bulldozer has higher IPC than our current architecture?

Is somebody being paid by intel to continually post these statements?

[slaveondope]

How many times do I have to tell you that bulldozer has higher IPC than our current architecture?

Is somebody being paid by intel to continually post these statements?

One starts to think so

[mAJORD]

I dunno, but it's pretty amusing to watch.

I've made SS's of the posts for future sigability

[ajaidev]

How many times do I have to tell you that bulldozer has higher IPC than our current architecture?

Is somebody being paid by intel to continually post these statements?

Lies lies lies Intel does not payoff people ever since the huge court case

Just a few more times or may be AMD can preview BD here in XS that would be great too.... j/k

[R101]

How many times do I have to tell you that bulldozer has higher IPC than our current architecture?

Is somebody being paid by intel to continually post these statements?

Just tell me if it will have higher IPC for _single threaded_ work. It must have more IPC per core since it has two 'almost cores' mounted inside one.

I read this whole thread and am 20 times more confused about BD performance than before reading it

[-Boris-]

Just tell me if it will have higher IPC for _single threaded_ work. It must have more IPC per core since it has two 'almost cores' mounted inside one.

I read this whole thread and am 20 times more confused about BD performance than before reading it

We already have numbers on that! It has been all over the place, 10% lower performance per thread with two threads instead of one.

[Florinmocanu]

Just tell me if it will have higher IPC for _single threaded_ work. It must have more IPC per core since it has two 'almost cores' mounted inside one.

I read this whole thread and am 20 times more confused about BD performance than before reading it

That's a module mate. 1 core in that module has higher IPC than a Thuban core. Pretty simple. But, when both cores in 1 module work on 2 threads, than you loose 10% performance per core because of the shared components. In single thread scenarios, 1 of the 2 cores works at 100%.

[JF-AMD]

We already have numbers on that! It has benn all over the place, 10% lower performance per thread with two threads instead of one.

See, that statement is what gets people in trouble. Someone reads that statement and assumes 10% lower performance.

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

[generics_user]

We already have numbers on that! It has benn all over the place, 10% lower performance per thread with two threads instead of one.

ok now tell me how are they going to get 50% more performance with 33% more cores while dropping 10% single thread performance?

every single part of your comment is 100% wrong

[nn_step]

See, that statement is what gets people in trouble. Someone reads that statement and assumes 10% lower performance.

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

I'm guessing that they assume that you removed some under-utilized parts of the core, that performance would decrease; irrespective of any other changes to the core.

[informal]

See, that statement is what gets people in trouble. Someone reads that statement and assumes 10% lower performance.

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

No John,terrace and savantu just don't want to hear that. They will probably disregard your whole post and continue as before.

[BatteryOperated]

IGNORE SAVANTU AND TERRACE
I am not any kind of genius, but for the love of Pete...

There are only two examples in IC history where a product has been deliberately designed to be slower than possible.
1.) Intel Pentium 4
2.) The new SOC for Xbox360 combining cpu+gfx.

[-Boris-]

See, that statement is what gets people in trouble. Someone reads that statement and assumes 10% lower performance.

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

Then we phrase it like 11% more performance in single threaded apps due to the increased amount of resources the core gets when the other is idle.

ok now tell me how are they going to get 50% more performance with 33% more cores while dropping 10% single thread performance?

every single part of your comment is 100% wrong

10% more performance in one thread is compared to a module running two threads. 50% more performance with 33% more cores is a comparison with Magny Cours, both in multithreaded apps.

One is an number showing internal power differences, the other is a comparison with current processors.

[Calmatory]

Real soon there will be this magic touch...

I've seen it before, and it rocks!.

[geo]

stupid question: does 2 integer core means atleast 30% increase in performance comparing Intel Core to BD Module atleast going by this article
http://ixbtlabs.com/articles3/cpu/ar...2009-4-p2.html where an additional core (integer core in case of BD) adds about 39% improvement. sure there is slight single threaded perf loss, ipc improvements come into play and all that but...

[nn_step]

stupid question: does 2 integer core means atleast 30% increase in performance comparing Intel Core to BD Module atleast going by this article
http://ixbtlabs.com/articles3/cpu/ar...2009-4-p2.html where an additional core (integer core in case of BD) adds about 39% improvement. sure there is slight single threaded perf loss, ipc improvements come into play and all that but...

Here is what it means.

Bulldozer cores are like Intel Hyper-threading cores.

The primary difference is that AMD throws more transistors at the problem by giving each thread it's own set of integer execution units. Added to the fact that AMD’s distributed schedulers and instruction grouping. This is a clear architectural trade-off of performance and decreased control complexity versus size and increased execution complexity. Replicating two full featured ALUs uses more die area, but provides higher performance for certain corner cases, and enables a simpler design for the ROB and schedulers.

The honest truth is if NO CPU designed yet, can keep a constant throughput of 2 instructions per clock. So the more efficient design of the Integer cores, suggest that we shouldn't expect any performance drop at all. [For 99.9% of all user applications ]

[Dimitriman]

All the improvements done together with the frequency increase are meant to compensate the 3rd unit. You have the information in the AMD slide ( ...without significant loss on the serial single-threaded workloads components ), you also have the comments of M. Alsup ( ...and
loose a little architectural figure (5%-ish) of merit due to the
microarchitecture ). It all fits together now, irrespective of what marketing is trying to portray.

Someone please explain once more to these two terrace and savantu that when AMD speaks of tradeoffs, they do so on Bulldozer vs. Bulldozer, meaning 5% less performance on a BULLDOZER core with 2+2 ALU/AGU vs. a BULLDOZER core with 3+3.

I think some people can just be too blind in denial or wishful thinking, plus it drives me nuts how one can hug the nuts of one single company so tightly it feels like were talking about football rivalry.

You should grow up and learn to support healthy competition above all, you have NOTHING to gain if Bulldozer completely fails.

[informal]

You should grow up and learn to support healthy competition above all, you have NOTHING to gain if Bulldozer completely fails.

Not in a case when terrace is a shareholder in certain company . IF BD fails(it will not,but for a sake of an argument) the stock in that company raises and he profits.Simple math

[Calmatory]

You should grow up and learn to support healthy competition above all, you have NOTHING to gain if Bulldozer completely fails.

Intel stock, money. Didn't one Intel-biased former member admit that he had Intel stock and thus wishes the best for Intel to justify the AMD trolling?