AMD's Bobcat and Bulldozer

[generics_user]

Quite interesting, by that definition he wasn't a trol lat all. He provided a logical argument/question with some facts (even when they where old), yet people had no real facts to counter his spesific question (ST IPC). The only facts that where available where increased ST performance and increased IPC (not specifed if its ST or not).

Anyway personally I prefer hard numbers, so all this theoretical mindgames arn't my cup of tea.

only that every "fact" he postet was already debunked several posts earlier (actually in the BD news in the OP)

the 2 AGU / 2 ALU isn't genuine at all as the new units made Bulldozer wider than K8 was which was able to do only a total of 3 AGU / ALU operations at the same time; Bulldozer is cap able of doing a total of 4 agu/alu operations at the same time

additionally Single threaded IPC has to increase to make 8 cores running at 90% of their peak performance (each core in a BD module, when both cores are fully utilized, runs at 90% of the performance compared to a single BD core with an unutilized second core in its own module)
so all cores in the 150% faster statement by AMD have to run at only 90% of their peak single thread performance, which makes calculating single thread IPC even more complicated than ever before

[JF-AMD]

thanks for the update from round 2, i was waiting for this, he posts a thread in the AMD section, but im too busy here to check it out every 5 minutes.

the round of questions do provide some more fun info, and the comments are where the real goodies show up across the next few days

I post it in the AMD section because it is a blog, not news. I don't want people accusing me of being a spammer. I will leave the news posts for when we actually announce something

[gallag]

I for one think that Movieman was more than patient with that due.Actually that is an understatement

You are actually the worst troll on xs, You constantly complane about people trolling and yet all you have to do is look at your own post history http://www.xtremesystems.org/forums/...rchid=20942262 Do you agree that you are trolling far more in the anand sb preview thread than the guy you are complaning about here did in this thread? We can compare posts and see who stuck to the topic in hand with there posts and offerd rebutels relavent to the subject, And who did not.

Its the same people trying to turn XS into the zone, You guys hate any negitive input in any AMD thread but just look at your posts in any Intel threads, Dont take my word, Just look.

[god_43]

why cant we just let this thread die already...geeez gallag take it to pm man!

[Particle]

Quite interesting, by that definition he wasn't a trol lat all. He provided a logical argument/question with some facts (even when they where old), yet people had no real facts to counter his spesific question (ST IPC). The only facts that where available where increased ST performance and increased IPC (not specifed if its ST or not).

Anyway personally I prefer hard numbers, so all this theoretical mindgames arn't my cup of tea.

Just so we're 100% clear, I wasn't talking about this specific case. I'm only commenting on "trolls" in general as I find them as annoying as they are pervasive.

[gallag]

why cant we just let this thread die already...geeez gallag take it to pm man!

Hit a nerve? Again, Just look at your post history, You are one of them, All pro AMD and anti Intel, I can understand you being pro AMD but I just hate the way you guys get on peoples cases for being negitive or simple not being over positive in AMD threads yet you will go into Intel threads and do it your self???

[informal]

gallag, I usually don't bother reading anything you post,it's just a waste of time .Paranoia level is high,i will give you that.

right that's what I thought, because otherwise we would be seeing zero increase from core 2 to sandy bridge as primarily only the logic and prefetchers were changed

There were many core level changes ,especially in the prefetch area,one of the weaker points of 10h cores.

[Olivon]

Fanboyz (AMD, Intel, nVidia ... whatever) are so boring ...

Is it possible to have a fair discussion here between open-minded people ?

[Hornet331]

only that every "fact" he postet was already debunked several posts earlier (actually in the BD news in the OP)

the 2 AGU / 2 ALU isn't genuine at all as the new units made Bulldozer wider than K8 was which was able to do only a total of 3 AGU / ALU operations at the same time; Bulldozer is cap able of doing a total of 4 agu/alu operations at the same time

Yes one module is capable of 4 agu/alu ops, but that requiers 2 threads. For single thread your down to 2/2, but with a fornt-end thats much more capable then that of K8

additionally Single threaded IPC has to increase to make 8 cores running at 90% of their peak performance (each core in a BD module, when both cores are fully utilized, runs at 90% of the performance compared to a single BD core with an unutilized second core in its own module)
so all cores in the 150% faster statement by AMD have to run at only 90% of their peak single thread performance, which makes calculating single thread IPC even more complicated than ever before

Your making a mistake, your talking about relative performance, which is not related to IPC at all or is only one part of the equation.

[gallag]

gallag, I usually don't bother reading anything you post,it's just a waste of time .Paranoia level is high,i will give you that.

Is that the paranoia about Intel paying of anandtech you like to bring up in Intel threads when you are trying to be negitive, Could you just try not being a hypocrite? Stop going into Intel threads just to be negitive or stop complaning when people do it to AMD. And anyone can see I am not talking shi2 or being paranoide, All they have to do is look at your post history, Its not my opinion, Its all there in black and white.

I will not ruin this thead anymore, A lot of good info in it and it would be a shame for it to be locked so all I am saying is think about it guys, Are you what you say you hate?

[informal]

What paying up of anandtech,what are you babbling about? Where did i say that in the thread you mention?You are lost. The review @ AT was quite good .
Denial is just a one symptom of paranoia btw.

A lot of good info was lost in between 50 posts terrace alone produced in this thread,posts that were basically a beating of dead horse,posting questions that can't be answered here or even if they were(like JF did) the answers would be disregarded and trolling would continue.

Yes one module is capable of 4 agu/alu ops, but that requiers 2 threads. For single thread your down to 2/2, but with a fornt-end thats much more capable then that of K8

We don't know that for sure. And what was K8 capable in theory and what was possible in reality are 2 different things.

[radaja]

gallag so true

[Hornet331]

We don't know that for sure. And what was K8 capable in theory and what was possible in reality are 2 different things.

Why its on the chart?

Sure the forntend remains and is capable of decoding 4+1 instructions, but for singelthread int workload one core only has 2alu/agus.

There is no way bulldozer can fuse the int cores to make it act like a virtual 4alu/agu core, afair even JF denied this in this thread.

[informal]

Why its on the chart?

Sure the forntend remains and is capable of decoding 4+1 instructions, but for singelthread int workload one core only has 2alu/agus.

There is no way bulldozer can fuse the int cores to make it act like a virtual 4alu/agu core, afair even JF denied this in this thread.

There won't be any "fusing" of the cores,that's not possible. But AMD is not disclosing all the details such as ,why they now call the 2 pipelines Agen?There was never in the past such a term in their diagrams.It's has always been AGU and this was paired with 1 ALU,with separate schedulers.Now we have unified scheduler and this new Agen unit ,outside of L/S unit that is also on the diagram(standing separately too).And finally we have 2 additional integer units in the FPU .SO if you want to count it you can say its 2+2+1(2) in terms of integer execution power.

edit: the only "fusing" that may happen is in terms of FPU execution,when one core can use both FMAC units for itself.

[spursindonesia]

all i see is, AMDers are most likely proud of AMD's CPU mArch (sometime over optimist about it), and regarding Intel mArch, they admit its good but not ceding on Intel's superiority claim (sometime understating or underestimating Intel mArch capability). Intel trolls ? Well, nothing that AMD creates worth jacksh1t for 'em, that's one thing for sure. Sometime i'd like to think this forum drama as class struggle in life, beetween the bully haves and the defensive have nots, LOL.

[JF-AMD]

There won't be any "fusing" of the cores,that's not possible. But AMD is not disclosing all the details such as ,why they now call the 2 pipelines Agen?There was never in the past such a term in their diagrams.It's has always been AGU and this was paired with 1 ALU,with separate schedulers.Now we have unified scheduler and this new Agen unit ,outside of L/S unit that is also on the diagram(standing separately too).And finally we have 2 additional integer units in the FPU .SO if you want to count it you can say its 2+2+1(2) in terms of integer execution power.

edit: the only "fusing" that may happen is in terms of FPU execution,when one core can use both FMAC units for itself.

In current architecture our pipelines are shared between ALU and AGU. With bulldozer we actually break them out and make them dedicated, 2 for each.

Different engineers write things different ways. It is not that "AMD is changing what we call them" but that an engineer wrote it that way. Marketing tends to refrain from editing technical slides as they know more than us in that area.

[Hans de Vries]

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)


Regards, Hans

[Mechromancer]

^^^LOL! That is the most epic post EVER! So very very true.

[nn_step]

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)


Regards, Hans

Correction

while(!interrupted)
{
cout << "terrace215 post: " << random(bull_sh1t_reason) << endl;
}

[Movieman]

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

snip~
.....}
until (interrupt by Movieman)


Regards, Hans

Hello Hans.
Are you sure of all those names at the top of your post?
The reason I ask is that I got a "holier than thou" multi PM response from him after I removed his access to News and AMD section.
Yes, I chuckled too at your post!

Oh, forgot,no one drives me nuts. I just smile, grab my hammer and hit them upside the head so hard their grandchildren will walk with a 15degree list.

[informal]

"The more I post the more it decreases." part is the critical point the code above,cracked me up .
That was truly an epic post Hans

[Motiv]

In current architecture our pipelines are shared between ALU and AGU. With bulldozer we actually break them out and make them dedicated, 2 for each.

Different engineers write things different ways. It is not that "AMD is changing what we call them" but that an engineer wrote it that way. Marketing tends to refrain from editing technical slides as they know more than us in that area.

Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.

[Movieman]

Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.

I'll let you know when I get my hands on a pair of the unobtainable model 7196SE BD 16 core cpu's that run at 4GHz..

[AliG]

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)


Regards, Hans

you sir, have earned prime location on my signature.

It's free too! Gotta cherish those things as overclocking no longer is..

[Motiv]

I'll let you know when I get my hands on a pair of the unobtainable model 7196SE BD 16 core cpu's that run at 4GHz..

well they say it has a longer pipeline, so in my world...

..a longer pipeline means at least 5ghz on air *








*I can but dream