New AMD K10 45nm Revisions: Propus BL-C3, Regor DA-C3, Istanbul HY-D1

[zir_blazer]

I saw this CPU World article claiming that there are new Rev. C3 based Athlon II Processors about to be released (If they didn't already) and the OPN for those. Because of this, I decided to do a Google search and found this AMD PDF document with the info that I was looking for.

Added AMD Athlon™ Processor to Tables 5 and 20; Updated Table 6; Updated Constructing the Processor Name String; Added BL-C3 and DA-C3 silicon information to Tables 6, 18 and 19; Added erratum #383 and updated MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length) and MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status) for OSVW[3]; Added errata #408 and #437.

It was upgraded with those Revisions in January, so it is a bit old, but no one seems to have noticed it. Basically, the 45nm K10 Revisions (Or different physical Cores), was as following:


K10 45nm REVISIONS
HY-D0 (Istanbul) ---- 6 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / Only Opterons
RB-C2 (Deneb) ----- 4 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / PII, AIIX3 and X4
RB-C3 (Deneb) ----- 4 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / PII
BL-C2 (Propus) ----- 4 Cores, 512 KB Cache L2 por Core / AIIX3 and X4
DA-C2 (Regor) ------ 2 Cores, 1 MB Cache L2 por Core / AIIX2 and Sempron


The new releases introduces these new Revisions:


K10 45nm REVISIONS
HY-D0 (Istanbul) ---- 6 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / Only Opterons
HY-D1 (Istanbul) ---- 6 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / Only Opterons, MAYBE PIIX6
RB-C2 (Deneb) ----- 4 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / PII, AIIX3 and X4
RB-C3 (Deneb) ----- 4 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / PII, AIIX3 and X4
BL-C2 (Propus) ----- 4 Cores, 512 KB Cache L2 por Core / AIIX3 and X4
BL-C3 (Propus) ----- 4 Cores, 512 KB Cache L2 por Core / AIIX3 and X4
DA-C2 (Regor) ------ 2 Cores, 1 MB Cache L2 por Core / AIIX2 and Sempron
DA-C3 (Regor) ------ 2 Cores, 1 MB Cache L2 por Core / AIIX2 and Sempron


This means that you should look for these new Revisions when buying even Athlons II. Actually, that is where an issue comes up, AMD screwed the classic Processor Core identification process of the K8 era and now the only reliable way of knowing what actually the Core is seems to be looking at the Processor Stepping only. For example, my AIIX4 620 is Stepping CACYC AC, so it means that it is a Deneb (But I couldn't unlock the Cache L3, it doesn't boot up when I enable ASUS ACC and Unleashing Mode), yet the OPN is like any other Propus based AIIX4 620, AND even with CPU-Z or other tools the CPUID and Revision is that of a Propus instead of a Deneb!
This makes me wonder if there were any downgraded RB-C3 Cores that made they way to common AIIX4...

[Helmore]

You can edit the thread title yourself if you want to, just press edit, then 'Go Advanced' and then change the thread title.

Regarding comments, I'm not sure what to say about this. It's a nice find though.
I'm more interested in knowing when all their CPUs will start to make use of the refinements to GlobalFoundries 45 nm SOI node as introduced with Thuban. It should be interesting how far that will allow AMD to clock their quadcore CPUs. 3,6 GHz certainly seems feasible, but how much higher than that will AMD go?

[zir_blazer]

Done. Now, about the Thread itself, no one got comments??

[Behemot]

Phenom II X2's, X3's still could be unlocked?

[mAJORD]

C3 Propus and Regor.. good stuff.

Should see some higher stock freq models soon.. I guess.

[JF-AMD]

There is no Istanbul D1.

[Mechromancer]

^EXACTLY! I was about to post the same, but the credibility coming from the MASTER OF INSTANBUL himself should be enough. Thuban =!= Istanbul.

[Mats]

HY-D1 (Istanbul) ---- 6 Cores, 512 KB Cache L2 por Core, 6 MB Cache L3 / Only Opterons, MAYBE PIIX6

I'm pretty sure the X6 is E0.

[hollo]

cool, these http://en.wikipedia.org/wiki/List_of...sors#Athlon_II (as opposed to these http://en.wikipedia.org/wiki/List_of...om_II-based.29 )

[Hans de Vries]

I'm pretty sure the X6 is E0.

D0 = Istanbul
D1 = Magny Cours
E0 = Thuban


Regards, Hans

[RaV[666]]

Isnt magny cours a codename for two lisbon dies ?
If Thuban and Lisbon, are in fact different masks than im impressed.

[zir_blazer]

There is no Istanbul D1.

Looking at the same PDF...

Added AMD Opteron™ 6100 Series Processor, HY-D1 silicon information and G34r1 package information to Overview, Tables 4, 8-9 and 16-21; Corrected marking for errata #351, #355 and #383 in Table 20; Updated Table 6; Updated Potential Effect on System and expanded application of Suggested Workaround to additional processor types for erratum #405; Corrected and clarified erratum #383 Suggested Workaround; Added errata #406, #411, #417, #439-#441 and #443.

Well, Opterons 6100 are your very own Magny Cours so you are the guy to ask about it. Considering that HY-D1 is an improved silicon revision of the core that we call Istanbul (HY-D0), wouldn't it still use the same codename (Like the other ones, because as far that I know AMD didn't assigned new codenames to these Revisions), or what it is called as? I'm talking about the individual Core (As the phase "Two Istanbuls on the same package", that I think that Anandtech said it), not the entire Processor that is composed of two of those, that we know that is called Magny Cours.
I missed this though because none of the CPU-Z screens that I saw from Magny Cours had a Revision value.

D0 = Istanbul
D1 = Magny Cours
E0 = Thuban


Regards, Hans

I actually saw your Thread on AceHardware, but there is not any solid enough info about the Revision PH-E0 theory. Where the "PH" string comes from? I would have supposed that it would be of the HY family.

[Hans de Vries]

Isnt magny cours a codename for two lisbon dies ?
If Thuban and Lisbon, are in fact different masks than im impressed.

Lisbon is most likely D1.

The qualification of E0 for Server applications is an interesting thought
though presuming that the low-k dielectric process improvements for
the on chip wires came with the transition from the D1 stepping to the
E0 revision.


Regards, Hans

[Hans de Vries]

I actually saw your Thread on AceHardware, but there is not any solid enough info about the Revision PH-E0 theory. Where the "PH" string comes from? I would have supposed that it would be of the HY family.

It's this (from the 22th of March) what identifies Thuban as being an E-revision:

http://lkml.org/lkml/2010/3/22/336

From: Borislav Petkov <borislav.petkov@amd.com>

Starting with F10h, revE, AMD processors add support for a dynamic
core boosting feature called Core Performance Boost. When a specific
condition is present, a subset of the cores on a system are boosted
beyond their P0 operating frequency to speed up the performance of
single-threaded applications.

In the normal case, the system comes out of reset with core boosting
enabled. This patch adds a sysfs knob with which core boosting can be
switched on or off for benchmarking purposes.

Regards, Hans

[Movieman]

Any of you brain surgeons know if a 6168 mc can be unlocked?

[RaV[666]]

Any of you brain surgeons know if a 6168 mc can be unlocked?

There are no cores or cache to unlock.And multiplier unlocking isnt going to happen.Never heard of any K8-> multiplier unlock ,besides some weird occasions that chips shipped unlocked.
HTT should clock good tho.

[Movieman]

There are no cores or cache to unlock.And multiplier unlocking isnt going to happen.Never heard of any K8-> multiplier unlock ,besides some weird occasions that chips shipped unlocked.
HTT should clock good tho.

That's what I figured but had to ask
What do you think is a reasonable goal?
240-250?
We're talking air cooling here but good air.

[zir_blazer]

It's this (from the 22th of March) what identifies Thuban as being an E-revision:

http://lkml.org/lkml/2010/3/22/336




Regards, Hans

I readed it. But what I'm saying is that I don't get where the "PH" string in the PH-E0 revision comes from. If someone said that it is HY-E0, I would believe in it a bit more.
I still see hard to consider another silicon revision of a Core that may be physically quite similar or actually the same in a very little timeframe. Would AMD supercede it, or produce two silicon revisions of basically the same Core (Six Core, 6 MB Cache L3)? Considering that Magny Cours was released less than a month ago with the brand new HY-D1 Revision and yet we are going to see a new one in less than another month... It would make sense if they are using a different manufacturing process to adapt each one to a different market (Opterons are much more restricted by the power envelope, Phenom II X6 are not so much, besides they are going to scale quite a bit on Frequency).

[RaV[666]]

From my experience, amd SOI process clocks good until around 60C sometimes a bit more sometime a bit less.
In theory, these are two very thuban like dies, so cooled properly should do maybe around 3ghz,and more with good watercooling.
However htt clocking most of the time is easy up to 250mhz.For more you would need some nb ratios or nb voltage options.
They are doable in software on amd chipsets so in theory they can be changed in chipset registers.IF you would discover how to change all these things (and theyre changable with 95% certainty) you could go up to 400mhz HTT.Its important to remember that memory clocks are taken off HTT clock.So they have to be lowered before increasing HTT.

[Dresdenboy]

I readed it. But what I'm saying is that I don't get where the "PH" string in the PH-E0 revision comes from. If someone said that it is HY-E0, I would believe in it a bit more.

I think, the PH-E0 is based on this info:

AMD Family 10h (DR-Ax/Bx, RB-Cx, BL-Cx, DA-Cx, HY-Dx, PH-Ex):

http://www.hwinfo.com/

[zir_blazer]

*BUMP*

AMD PDF got upgraded. Thuban is Rev. PH-E0 after all. Looks like that was an accurate leak after all.

[madcho]

From my experience, amd SOI process clocks good until around 60C sometimes a bit more sometime a bit less.
In theory, these are two very thuban like dies, so cooled properly should do maybe around 3ghz,and more with good watercooling.
However htt clocking most of the time is easy up to 250mhz.For more you would need some nb ratios or nb voltage options.
They are doable in software on amd chipsets so in theory they can be changed in chipset registers.IF you would discover how to change all these things (and theyre changable with 95% certainty) you could go up to 400mhz HTT.Its important to remember that memory clocks are taken off HTT clock.So they have to be lowered before increasing HTT.

That's why i prefer black edition, not really expensive with multi unlocked.

Just add 200-400mhz without any change for your ram. Easy and let you have a very stable oc for nothing or almost.