VTT / VDIMM etc... Mythbust attempt

[M.Beier]

Well today Im launching a project... My HTPC is running following settings:

1.776v @ vdimm
1.1v VTT

According to XS, that should kill setup in matter of hours....

How long would ya like this to run, I bet it wont as much as damage a clarkdale....

Setup;
i5-650
Gigabyte GA-H57M-USB3
2x1GB D9GTR

133@160 bclk - 4ghz
2:10 (5x) - 800mhz 7-6-6-18
QPI: 2880*2 = 5760mhz (BCLK x36)

How long should this rig run in order to label it "myth busted".... And has to be on 24/7, or 4 hours a day for some months ok? : - )

[Hondacity]

those are safe imo...not going to harm the imc at all.

[M.Beier]

agree, however, often read more then 0.6v gab is certain death, I strongly disagree that claim =)

[SoulsCollective]

1.1vTT will kill a chip? Since when? Posted where?

The vDIMM seems a little excessive though, I doubt you actually need that much.

[dinos22]

stick 1.5vtt and 2.2vdimm
and you want to bust a myth with one setup....lol nice one

[overclocking101]

he means the general consensious that any more than .5/.6 difference between VTT and VDIMM on i7/i5 etc will kill the chip. it is said all over the place and lots of people are afraid to try it. one setup will not "bust the myth" but will show that it is possible just as the same testing on SKT775 45nm's did. no different here. im awaiting results and glad to see someone not afraid to try it out.

[Hondacity]

1.1vTT will kill a chip? Since when? Posted where?

The vDIMM seems a little excessive though, I doubt you actually need that much.

1.77 is actually just ok..some chips need extra voltage to achieve lower latency or a little more bandwidth

[mk-ultra]

1.77 sounds 24/7 to me

[miahallen]

agree, however, often read more then 0.6v gab is certain death, I strongly disagree that claim =)

Why? I'm not trying to argue...but why are you so certain?

[K404]

I'd like to see more testing on this Go for it Marc.

I think a lot of folk would like to know about vTT limits for 32nm chips. 1366 too

[Mean Machine]

I think you should definitely test this out at the Gigabyte P55 competition. To gather more data, I mean.

[saaya]

Well today Im launching a project... My HTPC is running following settings:

1.776v @ vdimm
1.1v VTT

According to XS, that should kill setup in matter of hours....

according to xs? who said that?
i created a thread about that myth almost 2 years ago and it was busted back then already... only a handful of chips died and its not clear why exactly... and most of them were early steppings too... c0 and d0 chips can take quite a large gap between vtt and vdimm... enough to not have to worry about it anymore i think. who would run 2.1v vdimm with 1.1v vtt anyways?
im curious how stable the 1156 chips are vtt to vdimm ratio wise, but id guess at least as strong as the d0 1366 chips.

[massman]

First of all, the myth has been busted already.

Secondly, if the setup doesn't die you've proven nothing because of the small amount of test sample. If it does die, you've reconfirmed the myth. So, there's no positive end to this thread (at least for you).

Thirdly, the VTT/VDIMM safety zone for Lynfield is TIGHTER than the one for Bloomfield. Apparently not many people are aware of this, although some hardware websites have made this public already. Just read this page: link.

Lastly, I don't mind this thread - it's always fun to see someone kill his rig on purpose

[[XC] Oj101]

1.77 sounds 24/7 to me

2.1v here

[M.Beier]

stick 1.5vtt and 2.2vdimm
and you want to bust a myth with one setup....lol nice one

2.56-2.6 VDIMM
1.72-1.76 VTT


@ P55A-UD6
But only for benching....

1.53 VTT
2.3 VDIMM
Hyper & X58..... Couldnt reach bachus though


Hmm, I guess I could up it a bit for this daily thing.... Would be around 2v for 6-5-5-18,,, I'll try later.

[Raja@ASUS]

As overclockers - we all acknowledge the variance between batches of CPU's and how they clock. The delta on some chips before the PNP FET's on the IMC transmitter stages go into avalanche breakdown may be a little higher than others as may be the level of reverse bias that the body diode can handle over the long-term before suffering damage. Does not mean to say it's not possible and a tolerance band based upon sound reasoning and design principals should not be cited.

I think much of the desire from overclockers to overturn what they see as 'myths' stems from a belief that more voltage is better to every single device regardless of it's function. While there may be areas of switching where raising rail potential gives back overhead, there are signaling stages that need to be approached in a more thoughtful manner - this is one of those areas.

For the sake of getting the very best from an IMC, you'd want to keep yourself away from 'effects' that ruin the way the IMC swings voltage - whether you get kicks from throwing caution to the wind or not.

[M.Beier]

As overclockers - we all acknowledge the variance between batches of CPU's and how they clock. The delta on some chips before the PNP FET's on the IMC transmitter stages go into avalanche breakdown may be a little higher than others as may be the level of reverse bias that the body diode can handle over the long-term before suffering damage. Does not mean to say it's not possible and a tolerance band based upon sound reasoning and design principals should not be cited.

I think much of the desire from overclockers to overturn what they see as 'myths' stems from a belief that more voltage is better to every single device regardless of it's function. While there may be areas of switching where raising rail potential gives back overhead, there are signaling stages that need to be approached in a more thoughtful manner - this is one of those areas.

For the sake of getting the very best from an IMC, you'd want to keep yourself away from 'effects' that ruin the way the IMC swings voltage - whether you get kicks from throwing caution to the wind or not.

Rajinder, its the desire for hard proves.... Or theoretical reasoning... I dont believen voltage is always better hence; VGDDR... (limited elsewhere)

- Can you enlighten everyone why the "caution" is needed on VTT / VDIMM?

[Raja@ASUS]

reverse bias and the possibility of body diode breakdown.

Read page 5 here for some insight: http://www.irf.com/technical-info/appnotes/mosfet.pdf

[Aerou]

Or maybe Marc is just making a lame excuse for being a junkie in need for some burned silicon?

[saaya]

Secondly, if the setup doesn't die you've proven nothing because of the small amount of test sample. If it does die, you've reconfirmed the myth. So, there's no positive end to this thread (at least for you).

well, its unlikely that the difference between the chips is huge, and its mathematically unlikely that he ended up with one of the rare best case or worst case chips, so its possible to at least get an idea of where the limit is... lets say his chip burns with a vtt/vdimm delta of .8v after a few weeks, then thats enough info to conclude that running more than a .6v delta isnt a good idea 24/7...
theres always SOMETHING, a rough idea, you can conclude from sample testing... but yes i agree, its far from enough to prove a myth exists or doesnt... as soon as .1% of cpus dies from a certain voltage setting, there will be several reports about it online, and the myth will live on...
thats something most people dont understand, the difference between 99% safe voltages and 100% save voltages is huge ^^

Thirdly, the VTT/VDIMM safety zone for Lynfield is TIGHTER than the one for Bloomfield. Apparently not many people are aware of this, although some hardware websites have made this public already. Just read this page: link.

wow i didnt know that... and yes, its not "xs" who came up with this myth, its intel... they were the ones who told several enthusiasts, the entire press, and all mainboard and memory makers of how sensitive nehalem based cpus are to a vtt vdimm delta. and they exaggerated quite a bit, probably to scare people... they originally claimed 1.8v vdimm with 1.1v vtt would kill a cpu within days if not hours. for some b0 samples that was actually true (happened with 2 chips at foxconn) but c0 was a lot tougher and d0 even more... i only heard of 2 d0 chips that MAYBE died from a bad vtt to vdimm ratio.

oddly enough, gulftown es chips seemed to have a very similar problem again, and again the retail chips seem ok...

i totally agree with the madshrimps article btw, how come intel still cant come up with a robust vtt/vdimm design like amd?

marc, id say go for voltages that make sense first.
push for the highest vdimm your mem still scales with under ln2, with high vtt... or maybe push vdimm even higher than it scales to check if higher vdimm is still ok.
then reduce vtt and see if a 1v delta is ok for benching several sessions.
if there is no degradation, then thats good news...
then test on air, again increase vdimm with vtt until it doesnt scale anymore, maybe a bit higher...
then reduce vtt...

i dont think that there will be degradation or dead chips from this... you probably have to run huge vdimm with ridiculously low vtt to run into issues... and that just doesnt make sense...
so even if you degrade or destroy a chip, its will probably be pretty useless cause nobody would ever run those voltages so far apart from one another...
all you would prove then is that its possible to kill a cpu with too high voltages... which is nothing new

[Mescalamba]

As much as I know, only A0 and B0 chips of i7 had this problem.. C0 and D0 are I guess fine, at least Ive runed them at 2.0V vDIMM and Im still fine.. but I keep 0.5V difference.. (well it is more stable so..).

I think that i5 is without problems in this, cause Ive seen really crazy voltages.. Dunno about i9 (or i7 980X as you want..).

As long as my rig is fine, I dont care..

[massman]

wow i didnt know that... and yes, its not "xs" who came up with this myth, its intel... they were the ones who told several enthusiasts, the entire press, and all mainboard and memory makers of how sensitive nehalem based cpus are to a vtt vdimm delta. and they exaggerated quite a bit, probably to scare people...

You're right, most likely ... but that's why I was so pissed of when I did the basic math for Lynnfield. If you want to scare off people, Intel should do it properly and not half-half, because now it looks like they have no clue what they're talking about. Also, I'm a bit sad that no other sites jumped on this topic ...

The fact that they were stressing the fact that Vdimm could kill a chip is, in my opinion, two-fold:

1) Before Core i7, even the normal enthousiasts were running 2.4V Vdimm on a daily basis as there are kits even rated at 2V+ stock. This combined with the no-knowledge of the electrical safety zone of VTT/VDIMM (IMC/MEM) could have caused a high RMA-ratio. And that's something Intel most certainly wants to avoid, for super-dupper obvious reasons.

2) More a personal opinion: when X58 was launced, memory manufacturers were challenged to bring triple channel memory kits. Given that a high voltage would result in a high RMA-ratio, I can imagine that Intel would very much like to push memory manufacturers to spend resources on developping low-voltage memory. By making a big fuss about the 1.65V limitation (yes - a lot of people are actually convinced that this is a vdimm limitation), they kinda forced the memory manufacturers to spend more time on the low-voltage kits and forget about the high-voltages ones.

Argument #1 is to make sure they don't lose money on RMA, argument #2 is to make sure they enforce other manufacturers to follow this requirement.

[Raja@ASUS]

All of the DC specs (voltage at pads) are given in relation to current draw vs frequency and is also shown with respect to power plane resistance (applied VID to VCC tolerance for motherboard designers), a simple change between series updates (current and frequency guard band) is enough to knock the max DC specifications table off and alter the load line tolerance tables. The rest is down to changes the internal bus I/O stages on the more integrated platforms and their associated current limits (not all of those are shown publicly by Intel). The only glaring omission from the current white papers is the VTT load line tolerance for the Lynn/Clark series of CPUs (although this would have been provided to sub-vendors).

[saaya]

All of the DC specs (voltage at pads) are given in relation to current draw vs frequency and is also shown with respect to power plane resistance (applied VID to VCC tolerance for motherboard designers), a simple change between series updates (current and frequency guard band) is enough to knock the max DC specifications table off and alter the load line tolerance tables. The rest is down to changes the internal bus I/O stages on the more integrated platforms and their associated current limits (not all of those are shown publicly by Intel). The only glaring omission from the current white papers is the VTT load line tolerance for the Lynn/Clark series of CPUs (although this would have been provided to sub-vendors).

so your point is... what?

massman, i think intel didnt realize people were running that high vdimm initially in the engineering process, they assumed stock voltages plus a safety range... then the sfety range ended up smaller than they planned for some reason and they realized people run a lot higher vdimm than specced... thats when they pushed not only memory vendors but even samsung elpida and others to work on low vdimm chips/kits...
initially intel even paid money to mem makers for releasing low voltage tri channel kits according to what ive heard back then they subsidized each sold low vdimm tri channel kit! i found it hard to believe, and still do actually... but i heard it from two seperate memory vendors...

[Raja@ASUS]

so your point is... what?

That Intel know what they are talking about (and that they don't pull these figures out of their a$$)