The GT300/Fermi Thread

[LordEC911]

Can you expand on this because leaving it like you did is very misleading since it isn't real 2bit ECC.

Also there are cases were AMD/ATi's ECC implementation will be better/faster than Nvidia's since in the case where Nvidia's ECC will actually try to correct the error and once it realizes it cannot be corrected it will still need to be flushed and redone.

[003]

Oh the Fermi is real! Just it's going to be a long wait if the Quadro Cards are not coming until Q2 2010

003 I am not sure if the Quadro Fermi clocks will be lower? (granted they might be on the memory), I am going by the Quadro FX5800 which had a Core Clock of 650Mhz compared to the GTX 280 which had a core clock of 600Mhz

Now, BFG will most likely do an OCX, Gainward a Golden Sample and EVGA a WTF, BBQ FTW edition with higher clocks, but the fact remains we have no idea whether the Quadro cards will be clocked higher, lower, or the same as the consumer cards.

John

I could have sworn reading a news article on this. I believe it was from BSN.

Ah, yup I am right. Here is the article in question. Some interesting quotes:

According to specifications based on NV100 A2 silicon [subject to change], C2050 will deliver 520 GFLOPS of IEEE 754-2008 Dual Precision format and 1.040 TFLOPS of single precision.

So yes it looks like the current numbers of 520 and 630GFlops are in fact based on A2 silicon, and A3 should up this considerably, as even Charlie admits in one of his latest editorials ("A3 will almost assuredly up the clocks quite a bit...").

First and foremost, Tesla is the slowest clocked member of Fermi-GPU architecture as it has to qualify for supercomputers. ... In order to satisfy the required multi-year under 100% stress, nVidia Tesla C2050/2070 went through following changes when compared to the Quadro card [which again, will be downclocked from the consumer cards]:

ECC will be disabled on GeForce cards and most likely on Quadro cards

Also there are cases were AMD/ATi's ECC implementation will be better/faster than Nvidia's since in the case where Nvidia's ECC will actually try to correct the error and once it realizes it cannot be corrected it will still need to be flushed and redone.

2-bit ECC is necessary for high precision HPC applications (i.e. medical imaging). ATI only has 1-bit ECC on the video memory, which isn't enough. Nvidia has 2-bit ECC on the video memory and the entire cache hiercharchy.

First you claimed you cannot "break" NDA.
Immediately after, you "broke" NDA by claiming that Fermi is significantly faster.

I am not the signer of the NDA, I know someone who is and NDA was broken when they talked to me. I will reveal general information that can't be traced back to the NDA signer. Whether or not you choose to believe me is out of my control. Irrelevant though as it will be revealed to everybody in Q1.

[[XC] gomeler]

First you claimed you cannot "break" NDA.
Immediately after, you "broke" NDA by claiming that Fermi is significantly faster.

To me, this sounds like a lot of hot air. If you want to be taken seriously, back up your claims with at least a tiny bit of evidence.

Or just drop the silly disguise that you know something more than then rest of us mortals, mr. Fanboy.

Don't feed the troll. Thought 003 was banned from XS News already

[ajaidev]

I could have sworn reading a news article on this. I believe it was from BSN.

Ah, yup I am right. Here is the article in question. Some interesting quotes:

So yes it looks like the current numbers of 520 and 630GFlops are in fact based on A2 silicon, and A3 should up this considerably, as even Charlie admits in one of his latest editorials ("A3 will almost assuredly up the clocks quite a bit...").





2-bit ECC is necessary for high precision HPC applications (i.e. medical imaging). ATI only has 1-bit ECC on the video memory, which isn't enough. Nvidia has 2-bit ECC on the video memory and the entire cache hiercharchy.



I am not the signer of the NDA, I know someone who is and NDA was broken when they talked to me. I will reveal general information that can't be traced back to the NDA signer. Whether or not you choose to believe me is out of my control. Irrelevant though as it will be revealed to everybody in Q1.

No ATI does not have 1bit ECC, it has a EDC based based on parity bit most likely. The ECC also use's EDC BTW there are two stages in how ECC works it detects then it try's to fix the error.

But if unsuccessful it requests the data again, EDC "In ATi's case" always requests the data again it does not try and fix the error. In a case where the error can not be fixed and timeout occurs EDC will be faster than ECC.

The only two things that fermi really has are a very flexable design, programmers can make it flip waffles and the fermi has a very nice FP64 FMA execution system...

[003]

No ATI does not have 1bit ECC, it has a EDC based based on parity bit most likely. The ECC also use's EDC BTW there are two stages in how ECC works it detects then it try's to fix the error.

But if unsuccessful it requests the data again, EDC "In ATi's case" always requests the data again it does not try and fix the error. In a case where the error can not be fixed and timeout occurs EDC will be faster than ECC.

The only two things that fermi really has are a very flexable design, programmers can make it flip waffles and the fermi has a very nice FP64 FMA execution system...

Ok thanks for pointing that out. It seems there are advantages and disadvantages to each implementation but ATI has no form of ECC/EDC on the cache. Also it will be irrelevant on the GeForce cards as ECC will be disabled.

[ajaidev]

Ok thanks for pointing that out. It seems there are advantages and disadvantages to each implementation but ATI has no form of ECC/EDC on the cache. Also it will be irrelevant on the GeForce cards as ECC will be disabled.

It most likely will be there people may soft mod it to get ECC. I hope its already started from first because from my experiance with the 5850's EDC really helps reach better freq/stability in memory.

Also i think the fermis approach to ECC is different than evergreens. Fermi ECC's the data present on the caches and the DRAM but not on the bus "Doing checks on both will add to lag among other things", evergreen doe the opp. it uses EDC on data in the bus not the data present on the cache or the DRAM.

I hope ECC is there in GeForce fermi's DRAM tough...

[fellix_bg]

The GDDR5 ECC implementation in Fermi is not exactly complete "by the book", as there is no dedicated ECC data bus in there. Instead of six 72-bit GDDR controllers (64 for data + 8 for ECC), Fermi dedicates part of the 64-bit data lanes for ECC encoding. That's why Tesla boards will see reduced on-board memory amount and some performance hit, when ECC is enabled.
In comparison, Core i7 have all of its three DDR channels being 72-bit wide, to accommodate full blown ECC implementation.

[LordEC911]

Thanks for the info on EDC/ECC. I knew there was more to it than that I just couldn't find the info anywhere.

[Vapor]

Cleanup #2 just went through. There's another ban + News section revocation.

Don't feed the troll. Thought 003 was banned from XS News already

Looking into it

[Chumbucket843]

having the bus on fermi 420 bits wide would probably made the die too big and even more costly in terms of bandwidth. gddr5 was not designed with ecc in mind either although nvidia uses edc which only protects reads along with ecc. they could have supported another memory interface but rambus is out of the question most likely and ddr3 is just too slow.

[Manicdan]

i think if everyone on XS pitched in and bought the forum mods each a Fermi, for all the hard work required to keep us clean, they would smash/burn/microwave it, just because it would bring back all the bad memories.

[Chumbucket843]

NVIDIA Fun Fact of the Week: GF100 graphics cards will provide hardware support for GPU overvoltaging for extreme overclocking!

how would this differ compared to software OCing?

[Solus Corvus]

Maybe there is a dial to turn or a button to push?

[highoctane]

I'm not interpreting that as something new to gt300 but more of a confirmation of function/capability.

As in hardware vrm that will be adjustable via software which we already have.

[Solus Corvus]

That's what it sounds like. And it's good news. I wonder what kind of headroom these boards will have.

[ajaidev]

With a default speed around 600-650mhz i really doubt it can reach speeds 5870/5850 can oc to core wise shaders is another thing.

[Solus Corvus]

It doesn't have to clock as high in absolute Mhz, as long as it can achieve a nice % over stock.

[BenchZowner]

If it hits 1.1GHz on LN2 then it will be very good

[annihilat0r]

http://en.expreview.com/2009/12/18/d...-not/6149.html

We have just been told by reliable sources that those benchmarks were exactly what NVIDIA showed AICs at the recent internal meeting. So, can we conclude the benchmarks are real?

[Helloworld_98]

by Reliable sources do they mean one of their Nvidia loving friends or someone holding an NDA for that product.

[nullface]

Jesus christ -> "The GT300/Fermi Thread"

[jaredpace]

I couldn't see nvidia using actual FPS numbers on benchmarks with 8xAA for a PR slide

also, fermi thread

[[XC] gomeler]

Merged to the GT300/Fermi thread.

[ajaidev]

If trues its great news 5850 will be priced lower than hell great DX11 card to start with.

[prava]

Mmmm haven't followed this thread for like a few days, any changes? Do we know anything besides the fact that they should be shown at CES Las Vegas? It's getting annoying to see a hell quantity of new posts only to find out that there are no news from the front...