AMD cuts to the core with 'Bulldozer' Opterons

[JF-AMD]

Sorry, I am on so many different forums that I forget to add a signature. I put in my standard one (that the lawyers want me to use...)

As to Bulldozer and chipsets, I can only speak to servers. Bulldozer will be supported by the same 56x0 chipsets that support Magny Cours, Lisbon and even our Istanbul today.

[Aerwidh]

Thanks for the info, JF-AMD

[BeepBeep2]

Thanks, JF-AMD and very intuitive posts. They do not seem biased either, they just sound correct.

[JF-AMD]

Believe it or not, the job of marketing is not to be biased. People see through that pretty quickly.

[BatteryOperated]

Believe it or not, the job of marketing is not to be biased. People see through that pretty quickly.

With Bulldozer, what is the point of Magny Cours?

[freeloader]

With Bulldozer, what is the point of Magny Cours?

Temporary solution until Bulldozer is ready?

[AliG]

Temporary solution until Bulldozer is ready?

that's as far as I understand it, something to compete with nehalem in the server department (I believe it has quad channel memory) until bulldozer comes in. If I recall, it actually scales quite nicely in terms of power consumption, and is a decent counterpart to Intel performance:watt

[informal]

MC = easier platform validation and preparation for seamless transition to BD based MPUs (and competing with Westmere based products in 2P and 4P until BD launches).
By the time BD based cores launch,both chipset and memory for it will be validated and the platform will be ready to roll with the new cores.

[Nedjo]

Temporary solution until Bulldozer is ready?

IMHO thats obvious: more performance than SocketF, establishing of the C32 and G34 platform that'll host Bulldozer, and creating bigger market for Registered DDR3 also can't be neglected!

[JF-AMD]

The Maranello platform (that supports both Magny Cours and Bulldozer) gets us to DDR-3. Our partners don't want to do a new microarchitecture and a new platform at the same time, so doing Magny Cours is the right move for them.

A 2-channel DDR-2 product would be very long in the tooth by the end of this year.

[mindfury]

Bulldozer=AMD's Netburst？

http://citavia.blog.de/2010/01/21/so...dozer-7850137/

All this info like the small L1 D$, 5 cycles latency increase for instructions with memory operands, longer latencies (+50%) for instructions compared to the previous architecture are further indications, that BD might be a high speed design. To those, who fear another Netburst: This might work out for BD due the very different characteristics of the 32nm process.

[Chumbucket843]

everything is hinting at high clocks so far. maybe 4-5GHz stock. a good comparison could be power7 rather than netnurst. AMD has been filing a lot of patents on silicon engineering lately. looks like they are focusing on dynamic power. that could hurt ln2 overclocking.

[Sparky]

everything is hinting at high clocks so far. maybe 4-5GHz stock. a good comparison could be power7 rather than netnurst. AMD has been filing a lot of patents on silicon engineering lately. looks like they are focusing on dynamic power. that could hurt ln2 overclocking.

True... not sure how it will affect desktop chips but at least for the opterons a lack of LN2 overclocking won't matter much. Servers are just simply too boring for that kind of stuff

[qcmadness]

No, it is actually a different design philosophy. AMD believes that based on the current technologies, the best way to solve multi-threaded problems is with more threads over more discrete cores.

In every architecture there will be shared and discrete components (look at L3 caches and memory controllers today). Within the integer core you can make resources either shared or discrete.

Shared resources need to be wide enough to allow for more throughput without bottlenecks or contention.

The challenge with hyperthreading (or SMT in the more generic sense) is that it's philosophy is about "filling the pipeline when one thread stalls" and not about driving better efficiency. In a perfectly efficient system, SMT would not be needed because there would be no gaps in the pipeline. (this world does not exist).

Think of SMT like carpooling. It may appear to be more efficient for 2 people to carpool to work and save money, but that depends on how far they live from each other and how far they live from work. Clearly if they live 3 miles apart and work is only 1 mile away, carpooling becomes less efficeint.

Having seperate cars may appear to be less efficeint, but if the car are hybrids and the carpool car was an SUV, suddenly the math starts to make sense.

The key with our architecture is that there are always cores always available (up to 16 per CPU). You won't find a case where you have 16 cores but you can only run 8 threads because the others are waiting for a chance to "jump in."

Long term, over time, you want to drive to greater CPU efficiency. Every time you increase efficiency with real cores, you have the potential to get more overall throughput. Every time you increase efficiency on SMT you may simply "squeeze the balloon." More efficiency in the primary thread means less opportunity for the SMT thread to "jump in" so you get a net zero gain in throughput.

So you mean AMD is going to scarify single-thread performance in favour for multi-thread performance in coming architectures?

And what is the estimation of transistor count for each module? About 160 mil?

[Dresdenboy]

So you mean AMD is going to scarify single-thread performance in favour for multi-thread performance in coming architectures?

Sounds like a core's clock frequency has to be constant all the time and that a core couldn't be powered off. But that's not the case.
And one of the knobs to increase single thread performance is a rather simple one, not requiring hundreds of engineers. Most XS members do that at home.

[savantu]

Temporary solution until Bulldozer is ready?

It better be. Storm clouds are beginning to appear over 32nm for the IBM alliance group. Whenever Intel presented a new process breakthrough, IBM soon followed with a press release in a "me too" fashion. The fact that they needed 18-24 months more than Intel to actually get the process working and release some actual parts was a second story.

Apparently the same happened on 32nm. The problem is bigger however : IBM has made a mistake or so believe other players in the industry. The gate first approach doesn't work. Nothing sucks than to find out you need to reinvent the wheel and start all over again developing a process. How much will it take ? 12 months maybe more, depending on how soon they deciphered and learned what Intel did and how to implement it in their own process.

What does that mean for IBM Alliance customers ? AMD planned to go with a very risky proposition : new uarch and new process. History tells us that is a lousy bet. Imagine the engineers from the Bulldozer team. They've designed the CPU based on given process characteristics, all their models and simulations. Now there is a chance everything might change. A bit nervous ? Of course they are silent at the outside; but I bet Bulldozer will fail to appear in 2011. Fortunately they have who to blame : IBM and GF.

Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore.

"My understanding is that the subsequent thermal steps are causing problems with the gate-first approach," said a senior vice president at Qualcomm Corp. (San Diego) who was attending IEDM. "GlobalFoundries seeks a gate-last approach, and if necessary they could drop in a gate-last module independent of IBM," the Qualcomm executive said.

Asked about the potential switch, a senior IBM technology manager said continuance of the gate-first approach after the current 32/28 nm generation is under review. Any shift to a gate-last approach, if it occurs, would come at the 22 nm node or later. "Both of the gate formation approaches have their problems, and there is no doubt that the gate-first approach is significantly simpler," he said, asking not to be identified. "For IBM, gate first will work well at the 32 nm generation, and I would not underestimate the power of incumbency, which could take it to the next (22 nm) generation. After that, we'll have to see what happens."

http://www.semiconductor.net/article...igh_k-full.php

Translation : yeah, it might work at 32nm, but obviously yields are down the drain. Exactly what foundries want to hear.
It is one thing to show a few transistors or a small SRAM from R&D, it's a completely different thing to get a production process ready to roll. IBM utterly sucks at the later.

[Particle]

I bet Bulldozer will fail to appear in 2011.

That's a pretty bold statement given the current indications that Bulldozers are heading for an early rather than late release versus their official late 2010 release date.

[Helmore]

savantu the optimist, that's for sure.

[Nedjo]

CPU based on given process characteristics, all their models and simulations. Now there is a chance everything might change. A bit nervous ? Of course they are silent at the outside; but I bet Bulldozer will fail to appear in 2011.

ah good old savantu! I knew someone is missing in this thread

[informal]

savantu the optimist, that's for sure.

My thoughts exactly

[Macadamia]

Hey lemme the same 1 "doom"y sentence from the same article written by the same source!

I can be an anal-yst now ey? XD


Oh BTW Intel can't even get the mobile Arrandales to perform properly (stuck at 1.8Ghz) on battery load, so much for static logic, high-k, and such a superior gate-first approach with smart core gating.

[freeloader]

Savantu is right. Bulldozer won't be ready in 2011, it will be available in 2010!

[Oliverda]

savantu is right. Bulldozer won't be ready in 2011, it will be available in 2010!

[Manicdan]

I can be an anal-yst now ey? XD

hey im an Analyst for real, and thats my joke, not yours. (show some respect to my kind of people)

[Helmore]

hey im an Analyst for real, and thats my joke, not yours. (show some respect to my kind of people)

Yeah, going anal deserves some respect.