AMD sheds light on Bulldozer

[PoppaGeek]

The TechReport

Incidentally, AMD put those recent 128-bit rumors to rest by saying Bulldozer's floating-point multiply and accumulate (FMAC) units will be able to process two 64-bit double-precision or four 32-bit single-precision operations simultaneously, but not single, 128-bit operations.

Are WCG WUs double or single precision? Are we looking at 2 WUs per core or 4 or am I not understanding this? The WUs are 32 bit right? Even with 64bit Boinc and OS.

[Chumbucket843]

no, thats just sse. 128 bit refers to the registers so on a single precision work unit bulldozer will work on 4 values in parallel like a gpu. sandy bridge will have 256 bit avx so it will be able to process 8 simultaneously and larrabee will have 512 bit so it will be able to process 16 values. each core has its own simd unit so if bulldozer is 8 cores then theoretically it will be as fast as sandy bridge clock for clock. i am pretty sure most projects are single precision. if cmt rumors are true then 2 wu per core for bulldozer.

[PoppaGeek]

OK still not understanding.

Article says 4 32 bit single precision per core and you say 4 values in parallel for single-precision but end it saying 2 WUs per core. Try dumbing down your explanation.

2 per core is cool and would make me happy, if affordable but trying to understand.

Thanks!

[lkiller123]

Well, it still won't happen until 2011

[informal]

no, thats just sse. 128 bit refers to the registers so on a single precision work unit bulldozer will work on 4 values in parallel like a gpu. sandy bridge will have 256 bit avx so it will be able to process 8 simultaneously and larrabee will have 512 bit so it will be able to process 16 values. each core has its own simd unit so if bulldozer is 8 cores then theoretically it will be as fast as sandy bridge clock for clock. i am pretty sure most projects are single precision. if cmt rumors are true then 2 wu per core for bulldozer.

Let's see: per "core"(the thing in my avatar) and in SIMD workloads, a BD core will be theoretically as potent as Sandy Bridge per clock,meaning it will be 256b AVX compatible .That's the thing with ISA extension set compatibility-you have to make it work 100% according to specs,and the specs are what SandyB. is having. The BD cores will have a FPU/SIMD unit capable of 1x256 or 2x128 (or 1x128b and other combos) mode operations.This is to cut power draw and optimize performance at the same time(since the 2 threads will be shared among the 2 int clusters and extract maximum ILP from SIMD code-similar to what intel is doing with Nehalem and future SandyB.;difference is the additional integer sharing hardware in AMD's approach).

@PoppaGeek

In blunt terms,theoretically the SIMD execution potential of one bulldzozer core will be 2x of the one based on Deneb(256b simd support Vs 128b one in Deneb). You can even see 2 128b threads running along the depicted BD core in my avatar .

[PoppaGeek]

Well, it still won't happen until 2011

Well I'll have Thuban to keep me warm and happy until then.

Thanks for explanation Informal and chumbucket.

[informal]

No problem .
One small addition,a picture is worth a thousand words :


Take notice of couple of things: Marketed 8 core(octal) BD based CPUs will have 4 modules each consisting of 2 integer clusters(or better worded: cores) capable of (naturally) 2 hardware threads and one 256b FP/SIMD unit capable of maximum 2 (but also only 1 if need be) simd threads! The efficiency of the SIMD unit will probably be even better than a hypothetical Deneb core with 256b wide SIMD unit since that same Deneb design would not be having dual threads extracting maximum ILP from SIMD code,like Bulldozer module will have .
The 4 module models will be marketed as 8 core chips since in essence they will be 8 core chips-and 8 threads will be present in Task Manager . This is somewhat similar to what we have with Nehalem but in Nehalem intel is not resource sharing the execution units the way AMD will be doing(AMD way: dedicated parts for some things like integer cores that can communicate ;one dual thread SIMD unit;shared front end and back end)

[Otis11]

Sweet! So this is gonna be good?!?

So, it has 8 threads on 8 cores? or is it 8 threads on 2 "cores"?

Is it just me or are they starting to blur the line between cores and threads...

[Movieman]

OK still not understanding.

Article says 4 32 bit single precision per core and you say 4 values in parallel for single-precision but end it saying 2 WUs per core. Try dumbing down your explanation.

2 per core is cool and would make me happy, if affordable but trying to understand.

Thanks!

Poppa, I'm with you. These kids are WAY too smart for me.

[lkiller123]

I am already confused by my homeworks, don't make it worse

[PoppaGeek]

Poppa, I'm with you. These kids are WAY too smart for me.

I wasn't too sure they were speaking English.

[xVeinx]

Sweet! So this is gonna be good?!?

So, it has 8 threads on 8 cores? or is it 8 threads on 2 "cores"?

Is it just me or are they starting to blur the line between cores and threads...

Threads would be a software term, core hardware (well, mostly). They are changing the structure of what we have traditionally conceived of as a core, sort of like the change to the GPU and the advent of stream processors. I don't think the terms are being blurred, but the mention of threads may become more prominent simply because it's easier for most to comprehend rather than the complex interaction between the newer modular form of the cores.

[STEvil]

A little bit of tweaking and you could use this as a form of speedup for single threaded apps.

[rcofell]

Sweet! So this is gonna be good?!?

So, it has 8 threads on 8 cores? or is it 8 threads on 2 "cores"?

Is it just me or are they starting to blur the line between cores and threads...

Imho I'd say 8threads on 8cores (in this section's context), since each hardware thread has a respective dedicated integer "core", which is essentially the basic requirement for having a thread; the FP unit could be viewed as just being an extension for each of these threads, since it can't independently support a thread on its own (no control instructions for instance).

Overall, it's certainly a novel concept that challenges the perception of what's a core, and the term module does more accurately represent the situation, although I'd still prefer the term core in some contexts :X

From my perspective it seems like it hinges on how tightly you couple the software concept of a thread to a discrete unit of hardware; you could say in SMT's case there isn't really a discrete unit of hardware for each thread, as it's all shared, but in this case each thread has its own INT unit, while the FP unit is shared between the two.

Anyways, it's mostly semantics... it is what it is

[Enoc]

this is from another forum , a member(oliverda) asking JF-AMD(John Fruehe, works in AMD server division)

So, if I'm not mistaken the quad, six or octal core (in the usual sense, so X4, X6, X8) Bulldozer CPUs will contain four, six, or eight Bulldozer module and the OS will detect these as octal, twelve or sixteen core CPUs. Am I right?

response.

No.

Interlagos:
12-core = 6 bulldozer modules
16-core = 8 bulldozer modules

OS will see 12 and 16 core respectively.

The Bulldozer module is a logical way to group components and allow for better power efficiency and a more modular scalable path.

[tbone8ty]

maybe a Deneb picture along side the Bulldozer pic would help?

[PoppaGeek]

maybe a Deneb picture along side the Bulldozer pic would help?

Probably not. All I asked was will it do 1 or 2 or 4 WUs per core. Not sure I have my answer yet. But if you have a pic of a Bulldozer CPU from ADM I am sure many here would like to see it.

[STEvil]

1 WU per thread

[lkiller123]

Wonder how much it will cost, hope to be in the sub-1k market.

[PoppaGeek]

I think I may kill myself.

How many WUs per core?
Not thread, not unit, module or Integer Unit or FMAC or anything else.

1 core = how many WUs run?

I may be stupid but this is a simple question or at least should be. A simple answer would be nice.

If it is a desktop CPU then AMD cannot sell it too high else people will just buy Intel. It either has to be faster or cheaper. I hope Thuban is less than $300. AMD goes higher than that for a CPU it will be out of my price range.

[Otis11]

Based on my limited knowledge I would say 1 WU per "core" since AMD does not have HT...

But there are 2 "cores" per bulldozer unit if I understand correctly?

[PoppaGeek]

One small addition,a picture is worth a thousand words :

Bulldozer's floating-point multiply and accumulate (FMAC) units will be able to process two 64-bit double-precision or four 32-bit single-precision operations simultaneously, but not single, 128-bit operations.

Let me try again using Informals pic.

In the pic there are 2 FMAC units. Article says, each FMAC unit can process 2 64-bit double-precision or 4 32-bit single-precision operations simultaneously. I stated I thought WUs were 32 bit single-precision. Right? So does that mean each FMAC unit would do 4 WUs? In the pic it looks like each core has one FMAC unit. I do not care about modules or threads. I do not care about games, benchmark programs or whatever else. WCG WUs.

How many WUs from WCG will run on one core? 1 core= 1 FMAC unit. The pic shows core 1 and core 2 and 2 FMAC units, one each core. 1 FMAC unit will run 4 32-bit precision operation.

I dunno if it is just the change in architecture, terminology or a lack of people reading the first post. I think Informal and Enoc may have answered this but I am not understanding so I appreciate their patience.

[Otis11]

One small addition,a picture is worth a thousand words :




Let me try again using Informals pic.

In the pic there are 2 FMAC units. Article says, each FMAC unit can process 2 64-bit double-precision or 4 32-bit single-precision operations simultaneously. I stated I thought WUs were 32 bit single-precision. Right? So does that mean each FMAC unit would do 4 WUs? In the pic it looks like each core has one FMAC unit. I do not care about modules or threads. I do not care about games, benchmark programs or whatever else. WCG WUs.

How many WUs from WCG will run on one core? 1 core= 1 FMAC unit. The pic shows core 1 and core 2 and 2 FMAC units, one each core. 1 FMAC unit will run 4 32-bit precision operation.

I dunno if it is just the change in architecture, terminology or a lack of people reading the first post. I think Informal and Enoc may have answered this but I am not understanding so I appreciate their patience.

Ah! Well for me it was just not understanding the question due to the new arch ad terminology... Honestly, this is nothing more than a guess, but looking at it, it seems to me that it could send a WU through each of those pipelines as long as they total less than 128 bits (which they do).

If so, this could be a beast of a cruncher... :drool:

Confirmation or refutation?

[PoppaGeek]

Ah! Well for me it was just not understanding the question due to the new arch ad terminology... Honestly, this is nothing more than a guess, but looking at it, it seems to me that it could send a WU through each of those pipelines as long as they total less than 128 bits (which they do).

If so, this could be a beast of a cruncher... :drool:

Confirmation or refutation?

Yeah that is why I am trying to understand it. From the way I read it 4 WUs per core.

[poke349]

Correct me if I'm wrong, but here's what I'm getting.

They're saying that the each core gets 2 threads. (like HT)

But unlike Intel, each core gets two integer units, and one FPU. Whereas each Intel core only has one of each.

So running integer heavy multi-theaded code will theoretically double the speed since each thread gets its own integer unit. But since both threads on a core share the same FPU, floating point won't be much faster.

But then when you factor in AVX, floating-point throughput will double.


I'm not too sure about the integer SSE unit... Is that also part of the integer unit? So will it also double in speed? Does that mean 4x faster when you add in AVX?