CPU GTL questions in P5Q Deluxe...

[Huexxx]

Hi,

i've been searching information about the GTL adjusting.

I've readed that, for 65nm microprocessors (like my Q6600), the CPU GTL levels must be 0.670x (67% of FSB Termination Voltaje), and for 45nm micros, the level must be 0.630x (63%).

With my ASUS P5Q Deluxe, we have two different things to adjust:

CPU GTL Voltage Reference (0/2)
CPU GTL Voltage Reference (1/3)

¿What does each parameter stands for? I think that the first stand for the first DIE of my Quad (two processors), and the second stands for the second DIE.

Then, acording to the information on GTL's depending the technology, 65nm in my case, both adjusts would be set to 0.670x.

Then, why are the standard values in P5Q Deluxe 0.630x and 0.670x respectively?

It's a bios error (ASUS error), or a personal conceptual error?

Thanks a lot.

[mikeyakame]

Next time you should probably post in the P5Q thread, or at least do a search for it but since you posted already. The reason you post in that thread is simple...it keeps all the information together for other users to find. Threads like this get lost over time.

Land assignment for GTLREF2 is located farther from the others, but I don't know conclusively this is the reason. My only conclusion is it's not a bios error rather to do with ASUS engineers design of the VRM and electrical traces. I can tell you from experience that the 0.63x and 0.67x for die 0 and 1 respectively work correctly on the P5Q. There must be a small difference between the voltages supplied to each die, and adjusting them with a higher value on die1 and lower on die0 has given me the best results for high FSB stability. So I can only conclude that ASUS engineers know what they are doing and did it for a reason! Equal values for both gave me stability problems on the P5Q i set up for a friend.

Q9000/QX9000 chips use a value of 0.667xVTT for GTLREF. I can find the value for the Q6000/QX6000 chips in the Intel processor datasheets but iirc they are exactly the same.

Each pair 0/2 1/3 consist of a two logical high/low signals for each die. 0 and 1 are address strobe logical high/low voltages, 2 and 3 are data strobe logical high/low voltages for die 0 and 1 respectively. I could have this back to front but for relevance of this discussion it's not important.

See attached jpg for gtl reference data. This is all I could find in the short time I've had to go through docs.

[Huexxx]

Thanks a lot... I'll post in the P5Q Discussion the next time...

Regards.

[jas420221]

I thought they were all a default of .67?

Ive seen people put up .63 before, but I just thought they were wrong.

[mikeyakame]

THey are all default 0.667 by Intel spec. Using a lower GTLREF voltage would attest to using a higher VTT to compensate. This is where a lot of people make the mistake of trying to set too low of a VTT voltage and get all kinds of stability problems when increasing FSB frequency. There is no problem using a low VTT voltage provided compensation to GTLREF voltage ratio is made.

Other factors come into play such as FSB_SWING which sets the limits for V(IL) and V(IH) as to be able to determine a logical high or low value. Logical High limit is set by VTT or V(IH) which is Input Voltage High, and Logical Low limit is set by VSS or V(IL), Ground or Voltage Input Low. GTLREF is taken as a ratio of VTT for a reference to determine where the Crossing point exists or where the Rising Edge of BCLK0 meets the Falling Edge of BCLK1, which is to determine the period of one clock.

On either side of the crossing point lies a crossing threshold after the differential voltage is switched to drive high or low. The threshold margin for ringback of BCLK0 or BCLK1 exists above and below the crossing point, where if the differential waveform falls in either region the signal becomes prone to ringback noise, or to put it simply this is bad!

There are also undershoot and overshoot values, which are either below V(IL) or above V(IH) respectively where the waveform can shoot past briefly. These two values are to allow for variances out of bounds which is normal for electrical components. Too far either way and bounce occurs. I can't explain this the best as I only know what I do from reading and little bit of engineering studies.

See the attached waveform graphs courtesy of Intel's excellent documentation. It might help make what I'm trying to explain a little less confusing. It was the most concise thing I could find!

On the top differential waveform graph, VH is Voltage High Input, which is generally close to VTT. VL is Voltage Low Input. GTLREF occurs at approximately the dotted lines where the Rising Edge Ringback lowest point is or the highest limit of the Ringback Margin exists. Between VH and Rising Edge Ringback Low or GTL Reference voltage is where the Waveform must generally occur for Logical High. The Same applies with Logical low but between VL and the lower limit of the Falling Edge Ringback. These two regions are where the clock waveform is required to exist to correctly determine where it is low or high. If the clock differential waveform falls beyond Overshoot, Undershoot or inside the Ringback margin bad things can happen, and generally it's instability, crashing, or what they call a FSB Hole at worst.

[jas420221]

See thats what I thought. There there isnt a right and wrong so to speak, the default value is ~.67.

[nullface]

So if i dont change VTT i should just let GTL alone?

Im on a E8400, should i set both GTL 0/2 and 1/3 to 0.63x as long as i dont change VTT (1.10V)?

[scharnhorst]

Hello,

sorry to ask but I'm not sure to understand very well the settings of GTLs.
I've got a P5Q deluxe + Q9650@4.23 GHz
I'm currently using the followings settings;
Vcore ; 1.29
Vfsb ; 1.28
CPU PLL : 1.52
GTLs CPU; 0.680 / 0.720
GTL NB : AUTO
As you can see I'm using high GTL. Is it risky?
I wouldn't like to use settings that could damage my CPU or my Mobo
Please any help would be appeciated.
Thank you in advance