why did pat gelsinger leave intel + some more idf infos

[saaya]

http://www.top500.org/blog/2009/10/0...ngs_and_goings

very nice read!
was wondering all the time while reading this article, wow this guys good, he knows his sht... who could it be? and... its a translation of none other than andreas stiller from c't

and NO, hes not related to ben stiller for those of you who dont know him

[Hornet331]

Nice read...
of summed up rumors about gelsinger and short briefing about the IDF topics... nothing new here, next please.

[saaya]

i found the background infos about pat and paul very interesting... and the analysis of intels top management and new structure...
i didnt know about the execution trace cache for example, and that itll be increased several hundred fold... so it seems to be VERY useful...
plus hes hinting that sandybridge and ivybridge wont be that interesting and haswell is the interesting part

[kl0012]

sandybridge and ivybridge wont be that interesting and haswell is the interesting part

I find it highly unbelivable that Intel will replace AVX by LNI. In my opinion it will be move back since LNI doesnt support 3/4-operand non-destructive instructions. Rather Intel will extend AVX to 512 or even 1024 bits (this option is already included in the specifications). Although I do not deny that LNI may appear in future versions of CPUs, definitely it wont be replacement for AVX.

Edit: My bad - LNI does supports 3 operand non destructive instructions. Still I wonder what opcode range it uses. Since LRB doesnt support regular SSE it is possible that LNI is mapped to SSE opcode range.