How Many Cores?!?!?!

[s7e9h3n]

Here's a little peek @ what's coming from AMD

http://valid.canardpc.com/show_oc.php?id=688110





Don't have much time for testing these days, but I'll try to squeeze in some benches...

[Smartidiot89]

Magny-Cours

But 10mb L3 isn't it supposed to be 12mb?

[Nedjo]

Magny-Cours

But 10mb L3 isn't it supposed to be 12mb?

probe filter takes 1 meg!

we need new rev of CPUz

[Smartidiot89]

probe filter takes 1 meg!

thanks

Shame this won't be a fun bencher as of now not many benchmarks can utilize this many cores and the clockspeeds are to low to show it justice... This has its home in a server.

Can you take a screenshot, or film it doing Cinebench? That would be :banana::banana::banana::banana:

[btarunr]

http://i.cmpnet.com/eetimes/news/09/08/AMD_chart.gif
probe filter takes 1 meg!

we need new rev of CPUz

That 1 MB is inaccessible so no point seeing it as 2x 6 MB L3.

[haylui]

Magny-Cours

But 10mb L3 isn't it supposed to be 12mb?

reserved 1 MB per CPU for the HT Assist

[sinar]

Is this come out from Austin or San Jose?

[wuttz]

Is this come out from Austin or San Jose?

64NOMIS says this comes out from the matrix.

[64NOMIS]

64NOMIS says this comes out from the matrix.

Hmph.

With this, who needs the matrix? You can just create a local server and run your own locally!

[wez]

[chew*]

S7 it's great to see your inevitable return. I think you need to shake off the dust on that cascade of yours bud

[zalbard]

Don't have much time for testing these days, but I'll try to squeeze in some benches...

NP, send it to me, I'll cover your slack!
Seriously though, that is pretty awesome.
0nm tech process is haxxor too!

[Sgt.McRuff]

So its using S890 north bridge. Then is it also on 45nm or 40nm proses? (the sr5690)
Still what is that like 17mb of cache, or 19mb if it has 12mb of l3.

[Lightman]

Glad to see you back s7e9h3n!

Regarding L3 cache - my suspicion is HT Assist taking the difference from 12MB L3. I know that for S1207 you can select amount of L3 assigned to HTA from BIOS.

BTW 0nm process roxx

EDIT: One thing catching my attention is Cache associative for L3! 96-way??? That would mean it is shared between all cores it's double of what Deneb have. Can't wait for some more details of implementation

[FlanK3r]

u must it bench a bit ....thx

[psyconut713]

did i read that right?

2 CPU's at 12 Cores a piece?

[Mats]

Nice post, s7e9h3n!!

0 nm is teh sh|t! Intel is waay behind with 32 nm . .

At first I thought it was some kind of Istanbul + Constantinople MCM, but it looks more like the real deal!

[s7e9h3n]

Thanks for the welcome back guys, although I must admit, I probably won't be hardcore benching for at least the time being as my work schedule doesn't really leave me too much time.....

did i read that right?

2 CPU's at 12 Cores a piece?

Yep, you did

[Lastviking]

s7e9h3n:

Nice to see you back again!...i was abit wory about you. And you come back with a nice cpu to

[[XC] Oj101]

http://valid.canardpc.com/show_oc.php?id=688110

How did you get the voltage to show in the validation?

And a BIG welcome back Stephan, AMD's missed you

[DedEmbryonicCe1]

How did you get the voltage to show in the validation?

CPU-Z 1.52.0+ shows the voltage in validation shots.
http://www.filehippo.com/download_cpuz/

[FlanK3r]

hehe, yes, new mosntrum CPU, where do u got it?

[EnJoY]

hehe, yes, new mosntrum CPU, where do u got it?

Newegg.

[demonkevy666]

this thread is going to get pommeled....

[FlanK3r]

Magny Course ES at newegg, lol ....