TSMC Joins CEA-Leti Program on Multiple E-Beam Lithography

[LowRun]

TSMC has signed an agreement with CEA-Leti, French semiconductor research institute, in which TSMC will join its industrial program IMAGINE, on maskless lithography for IC manufacturing.

This three-year program allows companies to assess a maskless lithography infrastructure for IC manufacturing and use Mapper technology as a solution towards high throughput. It covers a global approach, including tool assessment, patterning and process integration, data handling, prototyping and cost analysis.

http://techon.nikkeibp.co.jp/english...090707/172685/

[saaya]

maskless huh? mhhhh how would that work?
i thought without a mask you actually cant get as small structures onto the silicon as without it since the light acts as a wave to some degree and the mask acts somewhat as a lense?

[Shintai]

maskless huh? mhhhh how would that work?
i thought without a mask you actually cant get as small structures onto the silicon as without it since the light acts as a wave to some degree and the mask acts somewhat as a lense?

It only depends how "crude" your tools are. Thats why we use the masks today.

[saaya]

It only depends how "crude" your tools are. Thats why we use the masks today.

what do you mean with crude?
and who is we? i dont use any masks at all

[ajaidev]

maskless huh? mhhhh how would that work?
i thought without a mask you actually cant get as small structures onto the silicon as without it since the light acts as a wave to some degree and the mask acts somewhat as a lense?

I am also not sure how they can be done without masks but the effectiveness of the process is sure increased without a mask even if it means making the IC at a higher nm.

[flutie98]

The maskless part comes in by using a focused beam of electrons as the exposing energy (which hits a resist). This beam can be scanned across the wafer in the precious pattern wanted by using electronic pattern generators. The problem with ebeam litho since its conception is that since the beam is scanned to define the desired pattern, this is inherently a serial process and limits throughoutput massively compared to a Optical mask based litho where the entire pattern is exposed at once in a parallel fashion.

Ebeam litho however is still used extensively in the research and prototyping as its extremely quick to draw out a pattern in a CAD program and feed it into tool and have in-situ lithography done very quickly without the need to design a make an expensive mask set.

The article is about creating multi-beam systems that would add parallelism to the pattern writing process, and maybe increase the throughoutput to make this economically feasible in a production environment.

[saaya]

wow thanks a lot flutie98
makes perfect sense... and it sounds really promising actually, since you can have a variable exposure on tiny parts of the whole design!
im curious how big a problem it is though that the exposure to the photoreact is not happening at the same time for the whole wafer...

with electrons you can do a lot of cool stuff too that you cant do with light, theres already equippment that can shoot one electron at the time, the accuracy over light should be huge.

[flutie98]

wow thanks a lot flutie98
makes perfect sense... and it sounds really promising actually, since you can have a variable exposure on tiny parts of the whole design!
im curious how big a problem it is though that the exposure to the photoreact is not happening at the same time for the whole wafer...

with electrons you can do a lot of cool stuff too that you cant do with light, theres already equippment that can shoot one electron at the time, the accuracy over light should be huge.

The amount of electrons you pump into the resist to expose it (per unit area) called the Dose can be controlled incredibly accurate over the entire wafer with a simple picoameter.

Also its not the accuracy thats the benefit as both techniques can be aligned incredibly well nowadays with sub 100nm overlay accuracy. Its the achievable wavelength of incident radiation is the limiting factor of resolution, current optical wavelengths used for litho is 193nm and tricks are played to reduce linewidths. A focused ebeam can have a spot size as small as <1nm. I currently work at a university using a new Ebeam litho tool in which we have successfully written 8nm lines in resist.

[Chumbucket843]

dont they use electron beam lithography to make masks?

[flutie98]

dont they use electron beam lithography to make masks?

Yes

[saaya]

The amount of electrons you pump into the resist to expose it (per unit area) called the Dose can be controlled incredibly accurate over the entire wafer with a simple picoameter.

Also its not the accuracy thats the benefit as both techniques can be aligned incredibly well nowadays with sub 100nm overlay accuracy. Its the achievable wavelength of incident radiation is the limiting factor of resolution, current optical wavelengths used for litho is 193nm and tricks are played to reduce linewidths. A focused ebeam can have a spot size as small as <1nm. I currently work at a university using a new Ebeam litho tool in which we have successfully written 8nm lines in resist.

very interesting...

is it still a problem that the beam spreads out and isnt fully focussed?
since its electrons, couldnt you use a really strong magnetic ring to bundle them until they hit the photoreact and prevent them from spreading?

its too bad there is no photoreact that requires a critical mass of exposure to react and as long as its not reached it doesnt react at all... that would be another way to get rid of all the unfocussed particle noise around the beam center...

this stuff is really interesting...
and there people go saying we wont be able to shrink circuits below 12nm

[flutie98]

very interesting...

is it still a problem that the beam spreads out and isnt fully focussed?
since its electrons, couldnt you use a really strong magnetic ring to bundle them until they hit the photoreact and prevent them from spreading?

its too bad there is no photoreact that requires a critical mass of exposure to react and as long as its not reached it doesnt react at all... that would be another way to get rid of all the unfocussed particle noise around the beam center...

this stuff is really interesting...
and there people go saying we wont be able to shrink circuits below 12nm

Well a final magnetic lens does focus them together as tightly as can be, but remember you are now fundamentally limited by the amount of coulomb repulsion from such a high density of same sign charge. So decrease the density you say? Well thats true, however now your decreasing the dose, and increasing exposure times.... Life is always a trade off

Edit: Also just because we have written 8nm lines, doesn't mean the rest of the Si processing steps needed to make a working transistor are able to work with 8nm precision. <12nm is still going to be a massive hurtle

[saaya]

Well a final magnetic lens does focus them together as tightly as can be, but remember you are now fundamentally limited by the amount of coulomb repulsion from such a high density of same sign charge. So decrease the density you say? Well thats true, however now your decreasing the dose, and increasing exposure times.... Life is always a trade off

Edit: Also just because we have written 8nm lines, doesn't mean the rest of the Si processing steps needed to make a working transistor are able to work with 8nm precision. <12nm is still going to be a massive hurtle

ok, longer exposure time is a trade off, but thats something you can live with... if you parallelize the exposure well enough that shouldnt be a problem at all...
sure, its expensive and coomplicated and takes time... im just laughing at people who say it cant be done... ever... at all...

why is the hurdle at 12nm? what exactly is the limitation there?

[flutie98]

ok, longer exposure time is a trade off, but thats something you can live with... if you parallelize the exposure well enough that shouldnt be a problem at all...
sure, its expensive and coomplicated and takes time... im just laughing at people who say it cant be done... ever... at all...

why is the hurdle at 12nm? what exactly is the limitation there?

As far as I know 12nm is not a magic number, but as we get close to the 10nm mark we are talking about gate lengths and other dimensions that are just a couple hundred atoms, Im not sure current Si cmos fabrication can be pushed that far. It is however on the ITRS roadmap for 2020, but only time will tell. My money is on a drastic shift from endless scaling of Si to a new material that is made larger, but can be used much faster.

[SnipingWaste]

We are reaching the end of Si and need a new material. The one that are out there being used have there own problems like Germanium, Germanium strained on SI, Si strained with SI, Gallium arsenide, Gallium arsenide strained on SI with leakage. One of the new materials that might work out is Carbon (plastics).