DFI x48 T3R + Kingmax 1600mhz= bad combo?

[TheMan89]

I got a Dfi x48 T3R and ddr3 2x1gb kingmax 1600mhz 7-7-7-20 mem. And i have spent over 15 hours just trying to get it to be stable at spec speed. But i cant get it to work. So now i turn to you experts out there that have the same memory sticks and a x48 board. I kindly ask you guys for help. I should relly need some help with the settings in bios for the memory.

I have managed to get it stable in super pi 1mb in 700mhz 8-8-8-24 (ddr1400) but thats all...

(sry for my bad english...)

This is how it`s set now:

DRAM Timing Page
Enhance Data Transmitting.................Normal
Enhance Addressing........................Normal
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................8
RAS# to CAS# Delay (tRCD).................8
RAS# Precharge (tRP)......................8
Precharge Delay (tRAS)....................Auto
All Precharge to Act......................7
REF to ACT Delay (tRFC)...................60
Performance Level.........................9
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................18
Rank Write to Read (tWTR).................13
ACT to ACT Delay (tRRD)...................4
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................5
ALL PRE to Refresh........................7

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DRAM CLK Driving Strength.................Level 6
DRAM Data Driving Strength................Level 8
Channel 1 Default Skew Model..............Model 3
Channel 2 Default Skew Model..............Model 3

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 469ps
DIMM 2 Clock fine delay...................Current 469ps
DIMM 1 Control fine delay.................Current 427ps
DIMM 2 Control fine delay.................Current 385ps
Ch 1 Command fine delay...................Current 413ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 602ps
DIMM 4 Clock fine delay...................Current 602ps
DIMM 3 Control fine delay.................Current 539ps
DIMM 4 Control fine delay.................Current 455ps
Ch 2 Command fine delay...................Current 392ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

Common CMD to CS Timing...................AUTO


It`s sp unstable that it freezes in the bios...