IBM 32nm Processors Sampling in Winter 2008

[Jaivan]

Chipmakers are always looking to move to smaller nanometer build processes. The smaller process allows them to get more chips on a single wafer and helps improve power efficiency and performance at the same time.

Current processors from Intel are using 45nm technology. IBM is leading an alliance of major semiconductor firms that includes Chartered Semiconductor Manufacturing Ltd., Freescale Inc., Infineon Technologies AG, Samsung Electronics Co. Ltd STMicroelectronics, and Toshiba Corp. in the development of a new High-K Metal gate material that promises to significantly improve the performance of microprocessors.

The new material being used is known as high-k/metal gate (HKMG) on silicon and is being manufactured at IBM’s 300mm semiconductor fab facility in East Fishkill, New York. The new HKMG process is allowing IBM to build circuits at 32nm. IBM says that this size reduction allows for 35% higher performance that similar chips made using 45nm technology. IBM also says that power savings on 32nm chips are from 30 to 50% compared to 45nm parts.

Gary Patton, vice president for IBM’s Semiconductor Research and Development Center said in a statement, “These early high-k/metal gate results demonstrate that by working together we can deliver leading-edge technologies that handily surpass others in the industry. Demonstrating this caliber of result in a practical environment means that as our collective client base moves to next-generation technology by using the 'gate-first' approach, they will continue to maintain a significant competitive advantage.”

IBM and its partners say that the new HKMG technology can be extended down to 22nm. This will lead to significant performance increases and power reductions in future chips made using the new HKMG technology.

IBM says that prototypes for the 32nm chips should be available starting in Q3 2008. Intel will be introducing its 45nm Nehalem chips later in 2008 and reports say Intel has plans for its own 32nm process in 2009.

Source

[cegras]

Whatever happened to the low-k proposed process? Mmph.

[Shintai]

How about they make 45nm first...

[saaya]

what ever happened to soi?
and what do they mean with sampling?
sampling as in sram? or sampling as in test logic? or sampling as in actual designs?

[Origin_Unknown]

How about they make 45nm first...

why? whats to say that they have to make 45nm?

[nullface]

why? whats to say that they have to make 45nm?

Second that, whats the point in making 45nm, when 32nm is possible?

[Shintai]

Second that, whats the point in making 45nm, when 32nm is possible?

Define possible. Actual product as in 2011 or so?

[BrownTown]

also, what does "prototypes" mean, we saw a 32nm Intel SRAM chips a LONG time ago, I'd bet they could make some sort of processor at 32nm by now if they *really* wanted, but there is a pretty big difference between being physically able to make something and being able to make it at an economical price

[savantu]

also, what does "prototypes" mean, we saw a 32nm Intel SRAM chips a LONG time ago, I'd bet they could make some sort of processor at 32nm by now if they *really* wanted, but there is a pretty big difference between being physically able to make something and being able to make it at an economical price

Prototype as in DSPs , stuff like that.

Being an alliance means you enjoy a few advantages and one heck of a big disadvantage : everyone pulls in different directions.

Some want low power (thicker gates , slower clocks ) , others want high performance ( thinner gates , higher clocks , high power ) , others want density above all ( memory makers ) and so on.

When you're alone ( like Intel ) you build a process for your design and viceversa , all of a sudden things become much simpler.You have far fewer tradeoffs to think about and all this saves time , money and more importantly gets you the best process for your products.

[ferrari_freak]

I thought silicon was only physically able to be made at a 32nm process so am I just really dumb or thinking about something totally different or what?

[BullGod]

Well loking at the companies involved we're most likely talking memory chips here. So don't hold your breath 'till IBM starts promoting a consumer chip again.

[FischOderAal]

I thought silicon was only physically able to be made at a 32nm process so am I just really dumb or thinking about something totally different or what?

last thing I read was <22 nm in 2016. but you need EUV for <32 nm.

feel free to correct me

[flutie98]

Whatever happened to the low-k proposed process? Mmph.

low-k dielectric processes are already being used, they a referring to the metal interconnect layers, not the FET gate dielectric layer

[flutie98]

last thing I read was <22 nm in 2016. but you need EUV for <32 nm.

feel free to correct me

remains to be seen if EUV is strictly needed for 32nm production, Intel has developed their 45nm process using 192nm Dry litho. While IBM and AMD has had to use 193nm Immersion litho for their 45nm process.