X48 Rampage Formula Preview.

[Zucker2k]

@ Mikeyakame

This is DRAM Static Read = Enabled
AiClock Twister = Stronger

Clockskews advanced 300 on A1/B1.

[safan80]

Zucker what is your vcore and NB voltage?

Ordered this board and will use it for my underutilized QX9770. I have 4GB OCZ Flex II PC2 9200 on hand and 2GB OCZ Flex XLC PC2 9600 on the way with the Rampage. I have read that before I fire this girl up, remove the NB heatsink and get rid of the TIM and reapply better stuff. I would want to know which water-block most are using as I will go with water-cooling off the bat. And what type of MOSFET coolers are people using when they remove the heatpipe?

Haven't seen too many pics in this thread. (though a little lazy to go through all 60 pages or so ... )

I'm using the mcw30 on my NB and I'm using the stock mosfet cooler with 2 140MM over the top of them.

[Zucker2k]

Zucker what is your vcore and NB voltage?



I'm using the mcw30 on my NB and I'm using the stock mosfet cooler with 2 140MM overthe top of them.

vcore is 1.384v - 1.400v (depending on OS - 32bit/64bit)

NB is 1.63v

[mikeyakame]

Zucker,

Thanks mate! I'm still trying to make sense of the MCHBAR register dumps for each clock twister setting, I've isolated the address ranges which appear to be related to the MCH <-> DRAM timings they affect but I've yet to figure out what all of them mean, but one thing I know for sure is that the address / data strobes are given higher delays with twister as it goes stronger.

CHA
FED14500 00000000 00000000 00000111 00007889
FED14510 00009635 00000CF7 00000425 00000010 <= 00009635 (see explanation for chb)
FED14520 00004280 00000203 00001B01 00001011
FED14530 00004333 00000924 00000924 00000800

These are related to CHA dram / mch handshaking possibly counters
FED14540 00000001 00000003 00001188 000044CF
FED14550 00000001 00007003 00001177 0000330F
FED14560 00000001 00006003 00001166 0000220F
FED14570 00000001 00005003 00001155 0000220F
FED14580 00000001 00004003 00001144 0000110F
FED14590 00000001 00003003 00001133 0000000F
FED145A0 00000001 00002003 00001122 0000000F
FED145B0 00000001 00001003 00001111 0000008F
FED145C0 00000001 00000003 00001100 0000000F

CHB
FED14900 00000000 00000000 0000AAB0 00002246
FED14910 00009434 0000020B 0000084E 00000052 <=== 00009434
||||_ dimm 3 clock fine delay ( dimm -> mch)
\ \ \ _ dimm 4 clock fine delay ( dimm -> mch)
\ \_ dimm 3 clock skew delay ( dram controller -> dimm)
\_ dimm 4 clock skew delay ( dram controller -> dimm , not 100% on these 2 values but I dont know what else they would be, and the first value changes with dram clock skew adjustments and ai clock twister light -> strong, 9 for strong, 8 for light)

FED14920 0000037D 00000004 00001B01 00001212
FED14930 00005542 00000924 00000924 00000C00



These are related to CHB dram / mch handshaking possibly counters
FED14940 00000000 00000000 00001188 000044CF
FED14950 00000000 00007000 00001177 0000338F
FED14960 00000000 00006000 00001166 0000330F
FED14970 00000000 00005000 00001155 0000220F
FED14980 00000000 00004000 00001144 0000110F
FED14990 00000000 00003000 00001133 0000000F
FED149A0 00000000 00002000 00001122 0000000F
FED149B0 00000000 00001000 00001111 0000000F
FED149C0 00000000 00000000 00001100 0000000F

[Shadowthor]

so the latest bios is still 0601?

[chris8325]

brand new - 0701 - but no changelog up to now

http://www.keepandshare.com/doc/view.php?id=941381&da=y

[mikeyakame]

ill flash it soon as I've finished installing windows updates
and post back.

i'll also do a binary compare between the previous 0501 and 0601 revs since i've got both handy and I spent the time figuring out what changed between 0501 and 0601 already.

gotta HEAD Off to work soon, so if i dont get it done before then, i'll do it a bit later on today

difference for 1B module between 0601 and 0701 is 659 : 723 bytes, reason being is the 1B module in 0701 is 54bytes bigger when uncompressed.

I'll need to disassemble the difference because these are much more than just cosmetic things like acpi compiler revision update.

Well i've flashed 0701 and visually on inspection all settings and their values appear unchanged. Memory bw in Everest is pretty close, and timings that are set through bios code are still as they were.

I'll update this post with any changes I find that are worth mentioning, mainly in 1B module.

[Brama]

Thanks mike........I am curious to see in which area they changed something.

[Zucker2k]

Awesome stuff Mike.

[jtf2]

okay im scratching my head now.
i have had this board running,on a hspc tech station,installed vista etc,waiting on water cooling parts.
i took off the nb hs assembly to reapply the tim,reaassembled,plugged everything in,restartedand now i am just getting a black screen,no bootup at all.
it starts up for a few seconds,turns itself off,restarts and just sits there!
what to do??

[Zucker2k]

okay im scratching my head now.
i have had this board running,on a hspc tech station,installed vista etc,waiting on water cooling parts.
i took off the nb hs assembly to reapply the tim,reaassembled,plugged everything in,restartedand now i am just getting a black screen,no bootup at all.
it starts up for a few seconds,turns itself off,restarts and just sits there!
what to do??

Are you getting a DETRAM on the LCD POSTER? If so, you need a cheap ddr 2 memory stick that'll do 1.8 - 1.9v. If it posts. go into bios and change vdimm to your liking.

[jtf2]

Are you getting a DETRAM on the LCD POSTER? If so, you need a cheap ddr 2 memory stick that'll do 1.8 - 1.9v. If it posts. go into bios and change vdimm to your liking.

i have mushkin redlines2x2 gigs,and they were working fine before.
lcd poster lights up cpu init,it did that before when it was working fine,now no go.

[Roger_D25]

Well you probably already know this jtf2 but make sure you have everything plugged in correctly (power connectors, HDD, RAM, etc...). Also make sure you have your graphics card, sound card, etc.. seated in properly to the motherboard. Hopefully it is something simple that is easily fixed because it would stink if you broke something during the process or removing or installing the heatsink. It would be quite easy to accidently break off a small surface mount component or other component on the PCB during this process but chances are good its something else. I just did the same thing a few days ago because the stock TIM and thermal pads were not properly applied. So I pulled everything off, cleaned everything up, and used some MX-2 on the NB and SB and made sure it made better contact with the heatsink. I also removed the upper heatsink/heatpipe assembly to make sure that all the MOSFETs were making proper contact with the heatsinks (thankfully my PCB is very flat even with my heatsink installed) so the contact was very good! Keep us posted on your progress because I'm curious as to what the problem is?

[jtf2]

i have removed the battery and i`ll try it tomorrow.everything was seated properly and connections were good.
i am going to reinspect for any missing pieces.
well i have to say i think its hooped!!
left the bateery out,inspected the board with a magniying glass,no missing pieces,that i can see or scratches etc.
the cpu light on the board does not come on at all.

[jtf2]

i have done some more reading abouth this cpu init error,
it is my understanding that during post if the ram is not getting enough voltage,it will take it from cpu,hence the failure.
i need to find a stick of ddr2 that can post with 1.6volts,
i am also going to do a full 24hr cmos clr,with the battery out,.
we`ll see what happens

[ElAguila]

Is the only difference with 701 bios that it lets you use the primary adapter without the black screen when you have 2 cards installed? I was wondering if it made any difference when oc'ing. If that is all that is fixed then it isn't worth it for me as I just moved the monitor cable to the other card. I am still on 0501 bios.

[DaLiu]

Does anybody know how to use Optical digital output from ASUS Rampage Formula, i have soundcard a Creative X-FI XtremeMusic and i bought a ZERO DAC preamp for my headphones and i would like to connect the preamp using Optical digital output but looks like is not working, anybody have any idea how to use it?

[mikeyakame]

Zucker and others.

Would you guys happen to know what type of eeprom chip the RF uses for bios? I've pulled my case apart a few too many times this week to open it up again today and check!

Need to get myself a few spare eeprom chips that I can use for testing bios modifcations. Friend of mine has a nice EEPROM writer with full PC software control so all I need are the chips to screw up, this way I don't need to damage my original Asus EEPROM and can throw it back in anytime!

Now the reason. I've finally got my head around the 1B and 21 MUI module interaction at bios setup level so I think I can successfully make some changes to the bios I don't plan to make my board unpostable by screwing up my original EEPROM testing with potentially broken bios code! Current public American Megatrends 8.0 tools don't work with the X48 bios' from what I can tell. I haven't successfully been able to load one up in AMIBCP yet, nor can I use the native ms-dos CMOS or DMI EDITOR from MSDOS 7.0, just says they are compatible with the bios. Funny thing is they handle P45 bios roms perfectly! Joys of high end hardware

What this means is I've had to get my head around what the AMIBCP UI does automatically, that is indexing the rom image and creating a tree of all the bios settings, setting their values, etc. It's so much harder to try and imagine how it looks and jump around a hex editor and doing data offset/index offset to track pointers and references! Comprehension is now there thougH, so I'm alot farther along the track than before thanks to Polygons amazing AMI reverse eng work he's done so far.

I've found something interesting with AI Clock Twister that appears to be transparent at least when AI Overclock Tuner is set to Manual.
AI Clock Twister has 2 Profiles for each selectable item, but these can't be manually set at present not directly. From what it looks like Profile 1 or 2 is selected by the Super MEM Profile menu option (AI Overclock Tuner ->). I'll confirm this when I get back from work later today need to check in bios. Heres the hex dump from Module 21 MUI.

Profile #1 :.Has lower DRAM latency.setting.Profile #2 :.Has higher DRAM.frequency setting..Note : Only valid.profiles can be.shown on the list

NB: The '.' is 0x0D hex, which is ASCII code for character return aka \n or newline.

Thing is this is linked to the Module 1B menu function index pointer array for AI Clock Twister so I need to investigate further and figure out whether adding an option to select profile manually from within AI Clock Twister works first and foremost and then makes any negligible difference to performance or stability!

[Zucker2k]

Zucker and others.

Would you guys happen to know what type of eeprom chip the RF uses for bios? I've pulled my case apart a few too many times this week to open it up again today and check!

Need to get myself a few spare eeprom chips that I can use for testing bios modifcations. Friend of mine has a nice EEPROM writer with full PC software control so all I need are the chips to screw up, this way I don't need to damage my original Asus EEPROM and can throw it back in anytime!

Now the reason. I've finally got my head around the 1B and 21 MUI module interaction at bios setup level so I think I can successfully make some changes to the bios I don't plan to make my board unpostable by screwing up my original EEPROM testing with potentially broken bios code! Current public American Megatrends 8.0 tools don't work with the X48 bios' from what I can tell. I haven't successfully been able to load one up in AMIBCP yet, nor can I use the native ms-dos CMOS or DMI EDITOR from MSDOS 7.0, just says they are compatible with the bios. Funny thing is they handle P45 bios roms perfectly! Joys of high end hardware

What this means is I've had to get my head around what the AMIBCP UI does automatically, that is indexing the rom image and creating a tree of all the bios settings, setting their values, etc. It's so much harder to try and imagine how it looks and jump around a hex editor and doing data offset/index offset to track pointers and references! Comprehension is now there thougH, so I'm alot farther along the track than before thanks to Polygons amazing AMI reverse eng work he's done so far.

I've found something interesting with AI Clock Twister that appears to be transparent at least when AI Overclock Tuner is set to Manual.
AI Clock Twister has 2 Profiles for each selectable item, but these can't be manually set at present not directly. From what it looks like Profile 1 or 2 is selected by the Super MEM Profile menu option (AI Overclock Tuner ->). I'll confirm this when I get back from work later today need to check in bios. Heres the hex dump from Module 21 MUI.

Profile #1 :.Has lower DRAM latency.setting.Profile #2 :.Has higher DRAM.frequency setting..Note : Only valid.profiles can be.shown on the list

NB: The '.' is 0x0D hex, which is ASCII code for character return aka \n or newline.

Thing is this is linked to the Module 1B menu function index pointer array for AI Clock Twister so I need to investigate further and figure out whether adding an option to select profile manually from within AI Clock Twister works first and foremost and then makes any negligible difference to performance or stability!

Interesting if you could pull that off; who knows, you might even be able to add other options by disassembling the Rampage Extreme's bios for example; I'm talking about stuff like cpu/nb skews, etc. My board is all tucked into my case and it's VERY crowded in there as I'm running a lot of hardware. Great findings though.

[mikeyakame]

I've already got quite a few bios roms sitting on my hard drive ready to be explored, an assortment of P5E and RE bios versions. Do you have the bios handy for the RF before Asus removed the tREF self-refresh timing setting? i think it was a beta of 0308 as official ASUS 0308 doesnt have the strings in the multi language module, and I know where there was a release with it working in bios. Worst case scenario I think I can code up a PCI Option ROM replacement module to check CMOS mask and change the value in MCHBAR but I rather not have to remove either a foreign language module or one of the marvell LAN boot roms. Losing the LAN boot in one of the onboard NIC's wouldn't be the end of the world if there was no choice.

Still would be easier to inject the original assembly instructions into the 1B bios core and 21 mui bins since their code did at one stage work!

If I was to get it working what do you think what would be the best way to go about it. Custom assembly code I'd basically have Auto where it reads DRAM frequency and calculates the correct tREF using the timing formula.

REF[t] = REFI[ns] / CK[ns]. Ie for DDR2-1200, tREF = 7800ns / ( 1000 / 600 ) = 7800 / 1.6667 = 4680T. For 7.8us refresh.
For 15.6us would be 2 * REF[t].

It'd be just a matter of allocating a CMOS mask that's free then or taking one that's not used. Simple case statement for comparing cmos register mask to fixed values, read MCHBAR chan a/b register, AND with mask, and write register at both offsets. Check it was succesful and return 0.

ASUS's assembly instructions would probably have less than half the size and be less cumbersome if I can disassemble them

Would be nice to have since there is clearly gains in latency when setting it through MCHBAR register in pci register writing tool or MemSET. Don't think it would be worth having a list of values to select from as every character is one less byte to use for instructions!

[Zucker2k]

I've already got quite a few bios roms sitting on my hard drive ready to be explored, an assortment of P5E and RE bios versions. Do you have the bios handy for the RF before Asus removed the tREF self-refresh timing setting? i think it was a beta of 0308 as official ASUS 0308 doesnt have the strings in the multi language module, and I know where there was a release with it working in bios. Worst case scenario I think I can code up a PCI Option ROM replacement module to check CMOS mask and change the value in MCHBAR but I rather not have to remove either a foreign language module or one of the marvell LAN boot roms. Losing the LAN boot in one of the onboard NIC's wouldn't be the end of the world if there was no choice.

Still would be easier to inject the original assembly instructions into the 1B bios core and 21 mui bins since their code did at one stage work!

If I was to get it working what do you think what would be the best way to go about it. Custom assembly code I'd basically have Auto where it reads DRAM frequency and calculates the correct tREF using the timing formula.

REF[t] = REFI[ns] / CK[ns]. Ie for DDR2-1200, tREF = 7800ns / ( 1000 / 600 ) = 7800 / 1.6667 = 4680T. For 7.8us refresh.
For 15.6us would be 2 * REF[t].

It'd be just a matter of allocating a CMOS mask that's free then or taking one that's not used. Simple case statement for comparing cmos register mask to fixed values, read MCHBAR chan a/b register, AND with mask, and write register at both offsets. Check it was succesful and return 0.

ASUS's assembly instructions would probably have less than half the size and be less cumbersome if I can disassemble them

Would be nice to have since there is clearly gains in latency when setting it through MCHBAR register in pci register writing tool or MemSET. Don't think it would be worth having a list of values to select from as every character is one less byte to use for instructions!

Couldn't a simple side by side comparison expose the differences between x48 DDr3 (RE) and x48 DDR2 (RF)? Maybe you're looking to go beyond a simple compariosn and replacing instructions/codes/registers that work with DDR3/components in the RE with the less sophisticated RF, you're actually looking to program your own stuff in, and may be tweak performance? I think the RE bios on a RF would be a blast enough.

[mikeyakame]

Couldn't a simple side by side comparison expose the differences between x48 DDr3 (RE) and x48 DDR2 (RF)? Maybe you're looking to go beyond a simple compariosn and replacing instructions/codes/registers that work with DDR3/components in the RE with the less sophisticated RF, you're actually looking to program your own stuff in, and may be tweak performance? I think the RE bios on a RF would be a blast enough.

Unfortunately can't use X48 DDR3 core bios code on X48 DDR2, they are very different with respect to skewing, ordering, strobe timing, and all that. Best I can do is disassemble both side by side and integrate functionality if possible, otherwise try and understand what the instructions are doing ans make them do it another way that works with the differences between the DDR2 and DDR3 memory controller.

I have no doubts that some things will carry between both bios' of the Formula and Extreme and I'm sure if I spend enough time understanding how Asus writes certain bios functions it can be easily done. Thankfully AMI 8.0 core hasn't changed much over the years, so the information available is still correct enough to figure out the minor changes pretty fast.

I've already figured out the 1B module segment pointers for cpu and nb clock skew, also made sense of the static menu arrays for the bios options, wellnearly all i've got that structure but 2bytes unknown right now.

[Brama]

Go on mikey!
Yesterday I put another 2x1 Gbyte memory sticks to reach 4 Gbyte (total 4x1 Gbyte) and my system is performing quite different than with 2x1 Gbyte. Now it is very hard to reach FSB over 450.

NB and cpu clock skew could help to reach a decent overclock.

[Zucker2k]

Unfortunately can't use X48 DDR3 core bios code on X48 DDR2, they are very different with respect to skewing, ordering, strobe timing, and all that. Best I can do is disassemble both side by side and integrate functionality if possible, otherwise try and understand what the instructions are doing ans make them do it another way that works with the differences between the DDR2 and DDR3 memory controller.

I have no doubts that some things will carry between both bios' of the Formula and Extreme and I'm sure if I spend enough time understanding how Asus writes certain bios functions it can be easily done. Thankfully AMI 8.0 core hasn't changed much over the years, so the information available is still correct enough to figure out the minor changes pretty fast.

I've already figured out the 1B module segment pointers for cpu and nb clock skew, also made sense of the static menu arrays for the bios options, wellnearly all i've got that structure but 2bytes unknown right now.

That's exactly what I was suggesting; but as you righly said, it boils down to knowing what instructions are specifically doing.

[mikeyakame]

So I've made a tiny bit of progress in the 1B module. Still not much considering i've spent over 10hours staring at it! Made a little more sense of the array structure used for the bios menu system, still got 2 word values i'm not quite sure what they are. I've been using the Maximus II bios, Rampage Formula bios and Rampage Extreme bios' to try and find common differences or similarities across all 3. The Maximus II P45 bios can open inside AMIBCP which sure makes it alot easier to run around a hex editor with since It shows the handle addresses for each item and subitem, and then a quick search in 1B locates the array for the menu ui.

I'll be making some posts over at Rebelshaven also when I figure things out to try and help Polygon along too, since his work is helpful to me also.

Before I can disassemble the 1B correctly I've still got to figure out the unknown two 2 words in the menu array as they are incremental between items and subitems, sometimes +1h, other times +4h or +8h or even +5h. Then there is what do they actually mean. I would imagine they are either an instruction pointer to an address on the stack, or perhaps a base pointer offset to another index?

Module 21 Header 00h-17h

474E 414C 5355 0400 1800 0000 FFFF 0000 FFFF 0000 A312 0000
00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h

00h-03h Dword Header Signature LANG (GNAL) in little endian signifies language mod
04h-07h Dword Module Runtime Location in little endian, 0004:5553, seg 4 offset 5553h.
08h-0Bh Dword Base Pointer Offset Bytes from 0 (18h or 24) 00000018h
0Ch-13h 2 Dword TUM Top Upper Limit of Memory ? Intel Architecture Design docs say something about this must be obeyed when in Real Address Mode for loading bios into Memory. Not 100%.
14h-17h Dword Offset to something! Still working on it.


18h is subtracted because
1) data starts at 18h
2) 04h-0Bh is a dword 0000000018h which is member of header struct that defines base pointer offset.

NB Clock Skew Menu Item Taken from RE 0901 bios.
Module 21
0x00007180
-> 7180h - 18h = 7168h -> little end -> 6871h
Module 1B
6871h is value of menu index ptr -> 093Ah
to get handle of menu array
093Ah - 18h
1b offset -> (0x093A - 0x18 ) / 2 -> 0x0491 -> little end 0x9104 -> menu string find -> 0191 04
0x36A13h

NB Clock Skew Menu Array
01 9104 F853 8102 9204 11 BC00 EC01 9304 9404 9504 9604 9704 9804 9904 9A04 9B04 9C04 9D04 9E04 9F04 A004 A104

01 9104 -> 01 Byte Menu String, 9104 Word -> little end -> 0491h [ offset to mul/sub to get pointer offset from 0 for string ] NB Clock Skew Menu String
F853 -> Word (still working on it?)
81 -> Byte mask for Menu flags, ie selectable, has help, has data with refresh, has static string, user select, superuser select, default is true, default is not true, is non selectable title, has data no refresh, etc.

02 9204 -> 02 Byte Help String, 9204 Word -> little end -> 0492h [ offset to mul/sub to get pointer offset from 0 for string ] NB Clock Skew Help string

11 -> Byte Count of Pointer Index's for Selections that follow.


BC00 -> Index Pointer to Auto string
EC01 -> Index Pointer to Normal string
9304 9404 9504 9604 9704 9804 9904 9A04 9B04 9C04 9D04 9E04 9F04 A004 A104 -> Index Pointers to Delay 100PS upto Delay 1500PS

This still confuses me when i look at it days later! haha Picturing a menu in hex code is still foreign to me!