dunnington is actually a socket 604 cpu, yes, pins, for boards like these..
Don't ask the cost! ($1180.00+ )
http://www.supermicro.com/products/m...7300/X7QCE.cfm
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jesus christ, i just came
DFI P965-S/core 2 quad q6600@3.2ghz/4gb gskill ddr2 @ 800mhz cas 4/xfx gtx 260/ silverstone op650/thermaltake xaser 3 case/razer lachesis
looks like Intel wants to keep the upper hand now
but well I am happy with my new c2d rig, so I will probably wait until the westmere die-shrink, by then DDR3 will cost as much as DDR2 now
6 GB Triple Channel with Imc goodness hopefully >20k read bandwidth
9x2GB DDR3 Triple channel integrated memory loving
---
I dont want to even know the costs of my future builds...I just want them now
-yonton228/timmy
Probably not on ATX boards. Still 6x2GB is a good thing.
Nehalem may double the available memory bandwidth on desktop platform, but dual socket platform is going to see really massive 4-5x improvement.
This should drastically help to improve SMP efficiency of dual Intel Xeon machines for HP computing, which is crippled now by extremely slow memory and inefficient memory controller.
256kb * 8 =2mb
you're basically thinking about it wrong though. Take todays core based CPUs, add in more cache to the l2 cache at a very slight penalty to latency(should be about as fast as 65nm l2 cache), very small.
then add in L1.5 cache which is somewhere between the speed of the l2 cache and the l1 cache.
you'de need DDR3-2500 for that(theoretically speaking, real world perf will always be lower). Not happening.
pipeline size doesn't matter so much for hyper threading. What does is available idle functional units. Longer pipeline did take up die space from alus fpus and the like, but in and of itself... well you get the idea
Last edited by xlink; 03-18-2008 at 01:48 AM.
That 2mb of L2 cache will not be the case in the early Nehalem cores and it might never even be released in a single socket form....
Triple channel DDR3-1333 is already at a theoretical bandwidth of ~32 GB/s and I bet the integrated memory controller on nehalem is a lot more efficient than on the current northbridge chipsets.
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By which wierdo math have you came to this conclusion ?
Triple channel means 3x the BW of a single channel.
DDR3 1333 offers 10.6GBs per channel ; or 32GBs per triple-channel.
That is now.
When Nehalem ships , DDR3 1600 will be mainstream , 12.8GBs per channel , 38.4GBs per CPU.
With 80% efficiency ( same as K8 IMC ) you're already over 30GBs of RAM BW.
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Current Phenom overclock
Max Phenom overclock
ahh thought it was bus speed * channel width not effective clocks * channel width
damned FSB.
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Nehalem actually steps one notch beyond the "native" quad-core design of K10, integrating the cache hierarchy more closely together, by making the L3 cache inclusive with the L2 arrays, thus allowing for shorter data-coherent update between the threads, just by picking an L3 cache line.
Of course, this comes at the cost of totally available L3 size, as follows: 8 - (4*256K) = 7MB. That's the reason for the rather shy L2 per core, not because of the pure low latency design intentions.
Read it again: inclusive relationship with the L2 arrays!Originally Posted by Cronos
Last edited by fellix_bg; 03-18-2008 at 03:49 AM.
I wouldn't be amazed to see 4GB sticks with ddr3, 2x2GB is the new 2x1GB with these ddr2 prices.
Nehalem is looking better all the time, can't wait.
Last edited by MGreg; 03-18-2008 at 03:16 AM.
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