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Thread: Intel Details Nehalem uArch Improvements - 256KB L2, 8MB L3 Confirmed

  1. #51
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    Quote Originally Posted by hollo View Post
    for lga775?
    Yes, Dunningham or whatever it is will be simply 3 penryns on one die with a built in l3 cache, this is no news, we've seen the die shot
    Quote Originally Posted by Hans de Vries View Post

    JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    .....}
    until (interrupt by Movieman)


    Regards, Hans

  2. #52
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    Quote Originally Posted by AliG View Post
    Yes, Dunningham or whatever it is will be simply 3 penryns on one die with a built in l3 cache, this is no news, we've seen the die shot
    dunnington is actually a socket 604 cpu, yes, pins, for boards like these..
    Don't ask the cost! ($1180.00+ )
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  3. #53
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    Quote Originally Posted by zanzabar View Post
    and dont forget that lga775 still has the hex core coming this summer and it should still oc well
    Hehe, no it doesn't. Dunington is dorp in replacement for Tigerton on socket 604, MP xenon servers, and it'll probably cost something on the order of $3K to buy a single cpu even if you have the 4 socket mobo
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  4. #54
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    Quote Originally Posted by Movieman View Post
    dunnington is actually a socket 604 cpu, yes, pins, for boards like these..
    Don't ask the cost! ($1180.00+ )
    http://www.supermicro.com/products/m...7300/X7QCE.cfm
    Argh I thought that was tigertown, too many code names. And now intel wants to manufacture SSDs and GPGPUs, man they might as well brew their own beer specificly for us xs geeks
    Quote Originally Posted by Hans de Vries View Post

    JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    .....}
    until (interrupt by Movieman)


    Regards, Hans

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    Mmm... pmos porter
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    jesus christ, i just came
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    looks like Intel wants to keep the upper hand now

    but well I am happy with my new c2d rig, so I will probably wait until the westmere die-shrink, by then DDR3 will cost as much as DDR2 now
    6 GB Triple Channel with Imc goodness hopefully >20k read bandwidth

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    i think in Q3 2008 all fellow XS WCG members will wet themselves
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    9x2GB DDR3 Triple channel integrated memory loving
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  11. #61
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    Quote Originally Posted by eva2000 View Post
    9x2GB DDR3 Triple channel integrated memory loving
    You got it...

    Looking forward to see more...

    Let the tweaking begin, when they arrive...

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    Quote Originally Posted by Den Leiw View Post
    looks like Intel wants to keep the upper hand now

    but well I am happy with my new c2d rig, so I will probably wait until the westmere die-shrink, by then DDR3 will cost as much as DDR2 now
    6 GB Triple Channel with Imc goodness hopefully >20k read bandwidth
    If it doesn't get over 30GBs I'd be really surprised.
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  13. #63
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    Quote Originally Posted by eva2000 View Post
    9x2GB DDR3 Triple channel integrated memory loving
    Probably not on ATX boards. Still 6x2GB is a good thing.

    Nehalem may double the available memory bandwidth on desktop platform, but dual socket platform is going to see really massive 4-5x improvement.

    This should drastically help to improve SMP efficiency of dual Intel Xeon machines for HP computing, which is crippled now by extremely slow memory and inefficient memory controller.

  14. #64
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    Quote Originally Posted by K404 View Post
    For nehalem- where are you getting the 2MB somewhat fast cache from?
    256kb * 8 =2mb

    you're basically thinking about it wrong though. Take todays core based CPUs, add in more cache to the l2 cache at a very slight penalty to latency(should be about as fast as 65nm l2 cache), very small.
    then add in L1.5 cache which is somewhere between the speed of the l2 cache and the l1 cache.

    Quote Originally Posted by savantu View Post
    If it doesn't get over 30GBs I'd be really surprised.
    you'de need DDR3-2500 for that(theoretically speaking, real world perf will always be lower). Not happening.

    Quote Originally Posted by AliG View Post
    I wouldn't say that, amd can't get their imc to clock well, but look at ibm's power6 monster, that is manufactured on a 65nm soi process with an imc and yet scales to 4.5ghz+ on air supposedly (though I haven't heard anything on the temps). As for hyperthreading, that failed previously because of the poor netburst design, the concept of it is quite good. Once multithreaded software appears more, you'll see the benefits, not to mention the much shorter pipeline to transfer data will help out with the hyperthreading usefullness
    pipeline size doesn't matter so much for hyper threading. What does is available idle functional units. Longer pipeline did take up die space from alus fpus and the like, but in and of itself... well you get the idea
    Last edited by xlink; 03-18-2008 at 01:48 AM.

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    Quote Originally Posted by xlink View Post
    256kb * 8 =2mb



    you'de need DDR3-2500 for that(theoretically speaking, real world perf will always be lower). Not happening.
    That 2mb of L2 cache will not be the case in the early Nehalem cores and it might never even be released in a single socket form....

    Triple channel DDR3-1333 is already at a theoretical bandwidth of ~32 GB/s and I bet the integrated memory controller on nehalem is a lot more efficient than on the current northbridge chipsets.
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    Quote Originally Posted by Helmore View Post
    That 2mb of L2 cache will not be the case in the early Nehalem cores and it might never even be released in a single socket form....

    Triple channel DDR3-1333 is already at a theoretical bandwidth of ~32 GB/s and I bet the integrated memory controller on nehalem is a lot more efficient than on the current northbridge chipsets.
    that's weird because it's called PC 10666 RAM because on a standard 128bit bus it's effective bandwidth is 10.6GB/s. Explain to me how a 192 bus will triple output over a 128bit bus.
    Last edited by xlink; 03-18-2008 at 01:59 AM.

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    Quote Originally Posted by anubis View Post
    i think in Q3 2008 all fellow XS WCG members will wet themselves
    Somehow I don't think it will take that long..
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  18. #68
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    Quote Originally Posted by xlink View Post
    ..



    you'de need DDR3-2500 for that(theoretically speaking, real world perf will always be lower). Not happening.

    By which wierdo math have you came to this conclusion ?

    Triple channel means 3x the BW of a single channel.

    DDR3 1333 offers 10.6GBs per channel ; or 32GBs per triple-channel.
    That is now.

    When Nehalem ships , DDR3 1600 will be mainstream , 12.8GBs per channel , 38.4GBs per CPU.

    With 80% efficiency ( same as K8 IMC ) you're already over 30GBs of RAM BW.
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    Quote Originally Posted by xlink View Post
    that's weird because it's called PC 10666 RAM because on a standard 128bit bus it's effective bandwidth is 10.6GB/s. Explain to me how a 192 bus will triple output over a 128bit bus.
    Currently the FSB is the bottleneck. And the FSB is half duplex and 64bit and running at 1066/1333Mhz.

    So he is right it is a tripple memory bandwidth of today.
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    Quote Originally Posted by savantu View Post
    By which wierdo math have you came to this conclusion ?

    Triple channel means 3x the BW of a single channel.

    DDR3 1333 offers 10.6GBs per channel ; or 32GBs per triple-channel.
    That is now.

    When Nehalem ships , DDR3 1600 will be mainstream , 12.8GBs per channel , 38.4GBs per CPU.

    With 80% efficiency ( same as K8 IMC ) you're already over 30GBs of RAM BW.



    Now all we need is HDD that can keep up with that. 100MBs aint cuttin it...



    So how many ram slots will be on each mobo? 6 or 9? mmmmm 6x2gb or 9x2gb DIMMs, goodbye pagefile!
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  21. #71
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    ahh thought it was bus speed * channel width not effective clocks * channel width

    damned FSB.

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    Quote Originally Posted by Jimmer411 View Post
    Now all we need is HDD that can keep up with that. 100MBs aint cuttin it...



    So how many ram slots will be on each mobo? 6 or 9? mmmmm 6x2gb or 9x2gb DIMMs, goodbye pagefile!
    I hear 6 for starters but don't be surprised to see 12 later on.
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  23. #73
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    Nehalem actually steps one notch beyond the "native" quad-core design of K10, integrating the cache hierarchy more closely together, by making the L3 cache inclusive with the L2 arrays, thus allowing for shorter data-coherent update between the threads, just by picking an L3 cache line.
    Of course, this comes at the cost of totally available L3 size, as follows: 8 - (4*256K) = 7MB. That's the reason for the rather shy L2 per core, not because of the pure low latency design intentions.

    Quote Originally Posted by Cronos
    No, total of 8MB cache is available.
    Read it again: inclusive relationship with the L2 arrays!
    Last edited by fellix_bg; 03-18-2008 at 03:49 AM.

  24. #74
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    Quote Originally Posted by fellix_bg View Post
    Of course, this comes at the cost of totally available L3 size, as follows: 8 - (4*256K) = 7MB. That's the reason for the rather shy L2 per core, not because of the pure low latency design intentions.
    No, total of 8MB cache is available.

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    I wouldn't be amazed to see 4GB sticks with ddr3, 2x2GB is the new 2x1GB with these ddr2 prices.

    Nehalem is looking better all the time, can't wait.
    Last edited by MGreg; 03-18-2008 at 03:16 AM.
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