Both Intel and Amd use SOI just applied diffrently afaik.
32nm will be offcourse with the high-k gate, since the second revision off 45nm will already be based on that tech. Atleast that's what I could summarize
Both Intel and Amd use SOI just applied diffrently afaik.
32nm will be offcourse with the high-k gate, since the second revision off 45nm will already be based on that tech. Atleast that's what I could summarize
Then it might as well be L2 cache, the whole point of cache hierarchies is that the lower levels of cache can be slower and therefore have higher capacities without jacking up the cost.Originally Posted by freeloader
Gigabyte MA790X-UD4P//Dell Latitude D620
Phenom II BE 940//Core 2 Duo 2.0Ghz
2x2GB OCZ Reaper//1GB PC5400
640GB WD Blue//80gb 7200 rpm hdd
Radeon 4850//Geforce 7300 Go
Hmm, not just that. The L2 is per core in these chips where as the L3 is shared allowing the cores to trade data. Having it at full (core) speed could have some advantages...
Serenity:
Core2 E6600
Abit IN9 32X-MAX
Corsair PC2-6400C4D
2x BFG OC2 8800GTS in SLI
Dell 3007WFP-HC
Immersion can go to 32nm already. From what im reading 22nm might be a possibility if better photoresists will get produced. With all the recent news about AMDs EUV tests there is a lot of speculation that AMD is targeting it for 22nm. Intel has dug itself into a hole here by not adopting Immersion at 45nm as they might have to switch again at 22nm to EUV and thats going to be costly(32nm(immersion), 22nm(EUV)). I also agree with JumpingJack that AMD seems to have stopped developing 65nm for a while now. There has been zero improvements in 65nm K8s and that says a lot.
Last edited by BrowncoatGR; 03-05-2008 at 09:55 AM.
Seems we made our greatest error when we named it at the start
for though we called it "Human Nature" - it was cancer of the heart
CPU: AMD X3 720BE@ 3,4Ghz
Cooler: Xigmatek S1283(Terrible mounting system for AM2/3)
Motherboard: Gigabyte 790FXT-UD5P(F4) RAM: 2x 2GB OCZ DDR3 1600Mhz Gold 8-8-8-24
GPU:HD5850 1GB
PSU: Seasonic M12D 750W Case: Coolermaster HAF932(aka Dusty)
as for as i know, intel uses the normal bulk cmos, not SOI
yeah intel uses bulk
You forgot to specify the year. My guess is 2015-2020. With lucky.
Friends shouldn't let friends use Windows 7 until Microsoft fixes Windows Explorer (link)
yeah I was getting confused about fd-soi as Intel did research into that before.
Are there any load pics? Why are there no 100% load pics when it's supposed to work? (taskmanager always around ~10%)
or am I blind?
OMG,it's a conspiracy!!!
Without the captured load bars in task manager we must conclude that AMD demoed unstable chips running at @2V with LN2..
/sarcasm off
Seriously,the first ES chips(45nm) are shipped to major partners for validation and testing,as of Febr. ...
Here is the load bars at "slightly higher" than 10% mark:
http://www.pcgameshardware.de/?menu=...mage_id=785536
Last edited by informal; 03-05-2008 at 11:52 AM.
Check the photo:
http://www.theinquirer.net/gb/inquir...amd-shows-45nm
About 270mm2.
Whoa, can you link me to a source?
That would be amazing if AMD could boost Shanghai's performance that high.
I've always wanted to go back to AMD, but unfortunately Barcelona wasn't tempting enough..
If Shanghai performs as reported though, I might just make the jump, then go back to Intel once Nehalem is on 32nm..
*Edit* Nevermind, found a link
Last edited by Carfax; 03-05-2008 at 01:33 PM.
Are you certain? I can understand a demo, but just a last month, AMD was saying 'we expect first silicon in January', first silicon in January to shipping sampling to customers is way way too soon.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Is DC 2 already implimented in Barcelona, or is that comming in Shanghai?
http://www.intel.com/technology/sili...ee/soi2000.pdf
I do not recall Intel producing any literature on FD, but they did do a pilot run on PD-SOI, from this they reported the same advantageous gains expected in SOI, but also concluded that it would not scale as well in later nodes:
Another SOI parameter that scales poorly is the history effect
on delay.This SOI vs Bulk debate was fought long and hard between Intel and IBM, Intel's argument was the the costs associated with going SOI were not justified, but my opinion is that there were probably also a stack of patents 10 feet high they would have needed to either a) work around or b) coughed up serious licensing dough that they simply stuck with bulk.100 nm devices described have the best Ion-Ioff characteristics
reported for 0.18 mm generation PD-SOI. SOI inverter delay of
7.4 ps is obtained at Vdd=1.5V and Lgate=100 nm. However, the
expected performance gain for PD-SOI diminishes dramatically
for 50nm devices due to (i) aggressive reduction of junction
capacitance for our bulk CMOS, (ii) the reduced impact of area
junction capacitance with scaling, and (iii) increased history
effect on delay for scaled Vdd
In any event, the 130 nm -> 90 -> 65 nm -> 45 nm (this one still a ?) scaling for SOI would appear to have validated thier position on the technical side.
It was a lot of fun watching IBM and Intel jocky and chest thump over this
EDIT: Intel is using SOI though for their silicon photonic wave guides : http://www.eetasia.com/ART_880035941...T_c75656df.HTM but this is out of complete necessity, you need a completely enclosed cavity to refract the light through the optical path, the burried oxide is needed to completely the enclosure.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Neither. Montreal will be the first MP product to feature HT3
Seems we made our greatest error when we named it at the start
for though we called it "Human Nature" - it was cancer of the heart
CPU: AMD X3 720BE@ 3,4Ghz
Cooler: Xigmatek S1283(Terrible mounting system for AM2/3)
Motherboard: Gigabyte 790FXT-UD5P(F4) RAM: 2x 2GB OCZ DDR3 1600Mhz Gold 8-8-8-24
GPU:HD5850 1GB
PSU: Seasonic M12D 750W Case: Coolermaster HAF932(aka Dusty
Could you post it please, I would like to read it.
Edit: It isn't this one is it? http://www.fudzilla.com/index.php?op...=5904&Itemid=1
Jack
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Wombat it would make those pic a whole lot more usefull if they included a result
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Thanks JumpingJack, was a good readup cleared some off my confusion
Though I can't read the article in your edit, I'll bookmark it and might sign up there tomorrow ( can't be arsed right now )
No it won't -- much like HT does not do a massive amount for K8/K10 in single socket DT workloads ... what it does do is allows the memory controller to be moved on die... which will provide a big difference. Thus, the memory access path is not in contention with all the other IO that might occur.
EDIT: CSI effective BW though will be much higher though ... http://www.realworldtech.com/page.cf...WT082807020032 David did a great job here picking apart Intel patents over the past several years to peice together some of the CSI technical details.
at 1333 Mhz, Intel currenlty provides peak BW of 10.65 GB/sec in one direction only.Initial CSI implementations in Intel’s 65nm and 45nm high performance CMOS processes target 4.8-6.4GT/s operation, thus providing 12-16GB/s of bandwidth in each direction and 24-32GB/s for each link [30] [33].
Last edited by JumpingJack; 03-05-2008 at 03:52 PM.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
No problem .. the article in my last edit was just a google on "Intel SOI Silicon Photonics" you will get several links....Thanks JumpingJack, was a good readup cleared some off my confusion
Though I can't read the article in your edit, I'll bookmark it and might sign up there tomorrow ( can't be arsed right now )
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Took me 5 clicks to get to this
How do you take the Vcore exactly?
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
My point wasn't is it accurate or not, even if it is... it is nothing to worry about or get excited about ... first silicon typically is way below targeted goals, it usually takes 2 or 3 revisions before final/retail silicon makes it.Read the post made by CPU-z author,below
Also look at the latest post made by wombat containing pictures of 16 cores machine utilizing Shanghais,now with VCore readings @1.15V.
The milestone here is not did they make a sellable part... the milestone is they show working silicon. This is about 10x more than what they showed for 65 nm ... heck, they launched 65 nm and it was a month or two later before anyone actually saw working silicon.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Yeah, in your link they used SOI to build # 2 in the cartoon about 2/3's down the article.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
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