All C0 Yorkfields have potential instability problem, confirmed by Intel

[btdvox]

Actually, you could do us all a favor and run prime95 for 48 hours and let us know... The errata is not entirely clear, the xbit article seems to suggest the lower end 4 layer PCBs can cause the problem.

However, I doubt you will see anything... it has been produced in the lab, and all the 9650 reviews, even the overclocking reviews, all claim stability even for the 4+ GHz OCs.

Errata, as mentioned above, are almost always over blown. Don't take that as they don't exist, but just because an errata entry exists does not mean that you will lock up ever day.

I understand it doesnt exist; in fact hey prob only saw it with a certain setup or set of motherboards but If I get any lock ups because of this- I will be dealing it- If it was a e8400 or a q6600 i wouldnt care as much but i spend a grand on this Chip.
that brings my next point- If somehow i do see something which i doubt, and if things go under my nose which is almost high unlikely as problems occur when you "notice them" lol,
What does intel do about this?

[btdvox]

So here is the story ... a rumor broke out end of november/beginning of december that Intel was delaying their quad launch. People speculated, there are wild rumors all over the net. Here is the Xbit article: http://xbitlabs.com/news/mainboards/...rocessors.html

Here is another speculations:
http://www.engadget.com/2007/12/19/i...mds-struggles/

Several stories were written, Xbitlabs has a unique story explaining that Intel discovered that if the FSB signal is marginal then the processor could lock up on lower quality boards, typically 4 layer PCB (el cheapo boards).

This makes sense... if the errata were a logic problem, then dual cores should suffer too, but for quad cores, there are two bus agents sharing the bus, think of it like you and your wife each using a hair dryer, run one hair dryer fine, but run them together .. pull down too much and trip a breaker. The extra core on the die adds an extra load to the bus, this will create a voltage drop... if the board does not have the margin for that voltage drop, then the voltages will not be enough to generate the appropriate differential to GTLref.

Your board is not in this class, you have no worries. You are getting worried over nothing. Question, does it boot? Have you run software on it?

Also, Intel publishes on a fixed monthly schedule... if any new errata are found, they will appear on the website under technical documents and specification updates: http://www.intel.com/design/processo...pdt/318727.htm



You probably had not heard of it because the Inquirer has not picked up on the update yet.

Jack

Lol third post in a row - Thanks though for the info I get it now- if the voltage is too low obv from die to die then errors will happen, But Wouldnt running Prime or Orthos find these instabilities like they do for everything else?

My system was as stated above has been primed for while to make sure of a good 24/7 overclock as I dont care to "push" the limits of my chip lol.
I decided to run a FSB of 400 instead of 300 (to get DDR2-1200) - I had it originally as QDR 1200 (FSB 300) to get 1:1 ram but wanted a little higher FSB lol- Glad I didnt go up to 420-450 which was my original plan Though im sure id still have no problems haha.

Thanks for the help.

[HDCHOPPER]

v-droop mods anyone?

[JumpingJack]

Lol third post in a row - Thanks though for the info I get it now- if the voltage is too low obv from die to die then errors will happen, But Wouldnt running Prime or Orthos find these instabilities like they do for everything else?

My system was as stated above has been primed for while to make sure of a good 24/7 overclock as I dont care to "push" the limits of my chip lol.
I decided to run a FSB of 400 instead of 300 (to get DDR2-1200) - I had it originally as QDR 1200 (FSB 300) to get 1:1 ram but wanted a little higher FSB lol- Glad I didnt go up to 420-450 which was my original plan Though im sure id still have no problems haha.

Thanks for the help.

To answer this takes a bit of understanding of bussing technology. Real quick -- I am writing this assuming you are not knowledged in the topic, my intentions are not to be demeaning in any way.

Parallel busses are just as they state, everything goes parallel. You have one physical wire for each bit, some timing lines, and voltage lines. However, parallel busses have a few draw backs, they generate EMI (electromagnetic interference) and can result in cross talk -- i.e. one wire will create inteference the trace right next to it. As the frequency goes up and voltages to drive it goes up, the risk for cross talk goes up. Study your motherboard, and look at the traces on the top layer... you will see some zigzag, loop around, wiggles .. these are design tricks to do primarily two things a) match the impedance for one line to all lines in the bus and b) break up any potential EMI due to running to many or to far (in length) in parallel.

The best example, in fact, are hard drives. The older PATA drives at 33 Mhz started with 20 pin IDE ribbons, as tech progressed, and drive/chipset vendors worked to increase data rates, the frequency and EMI on the 20 pin ribbon was too high, hence they went to a 40 pin ribbon, the extra 20 lines are simply duplicates of each line to carry more signal, to avoid x-talk. Ultimately, the PATA inteface simply could not be designed with high enough reliability at higher ferquencies, and problems (other than x-talk), drove the industry to serial comms for HDs.

The Intel bus is a 64 bit bus, meaning they pin up at least 64 lines between chpset and CPU, each clock tick will therefore send 8 bytes of data... as Intel ramps up the FSB, they also must contend with x-talk so little annoyances like this do not surprise me. Recall above, I mentioned wiggles and zigzags .. this is one reason why some MB makers OC FSB clocks better than others, simply better electrical engineering in stabilizing the FSB signalling.

Now, going away from EMI and x-talk -- parallel busses do have the advantage of enabling multple bus agents easily. As opposed to Serial busses which can also have multiple bus agents, but it is harder to negotiate on those busses, so many high performance serial interconnects are simply point to point (i.e. SATA ports only give one drive -- port replication is hard and expensive). This also allows Intel to package 2 die within the CPU and have uniform access to memory (we can get into all the pro's and con's of an MCM in a different discussion). Nonetheless, adding multiple bus agents to the parallel bus, there also must be mechansims to manage bus contentions ... i.e. the bus mastering algorithms must also account for traffic on the bus from all agents.

What does this mean, even if your processor is sitting idle, activity is occuring on the bus to manage any requests or status of the bus agents. Hence, my statement, you do not necessarily need to stress the CPU for this errata in order to trigger a physical marginality in the bus signalling.

If you built your CPU, and idled it and and stressed it and it is stable... you have no worries. In fact, to you should expect a lock up now and then ... I have never had a computer that never locked up or BSODed... but if it did, I don't go off to errata assuming the CPU is bad... it could have been any number of problems, usually software or it could have been hardware. However, the frequency of issues is nothing that is abnormal and unless it does it every hour on the hour (well, I exaggerate) say every few days... a random lock up here and there is nothing to fret over.

EDIT: I dug through some old favorites links and found some cross-talk, it is infact a problem in many facets:
http://www.sigda.org/Archives/Procee...iles/06c_2.pdf
http://dropzone.tamu.edu/~jhu/teachi...ngASPDAC01.pdf
http://www.sigrity.com/papers/2005/s17p6.pdf (Intel paper discussing power validation, but also briefly mentions info on crosstalk)

Jack

[HDCHOPPER]

THANK YOU JumpingJack !
thats why eye read these forums good info....

[btdvox]

^^^ Thanks for the explanation.
Yeah ive had the PC Idle for about 6-8 hours with no issues or lockups (assuming you mean freezes and needs a restart) Ive had some petty things happen but they have explanations-
The only main issues ive had are Prime 95 crashes when testing for stability (Which i was surprised as they werent BSOD's or freezes) I havent had a Prime 95 core fail though where the test would come up with an error just it crashing- I dont think this has to do with the issue though as it was most likely my CPU not being stable and needing more Vcore lol.
I will be doing my final stress using Prime 95 Blend today to make sure everything is ok.
Thanks.
(Is it odd that Prime 95 crashes and doesnt give an error? I had that happen 3 times, expecting a certain error (such as a rounding one etc)

[Cronos]

What does this mean, even if your processor is sitting idle, activity is occuring on the bus to manage any requests or status of the bus agents. Hence, my statement, you do not necessarily need to stress the CPU for this errata in order to trigger a physical marginality in the bus signalling.

I don't understand why are you insisting on the obvious and at the same time denies obvious.
In hypotetical absolute idle state (which is never happening in reality) you have your GTL voltage level always the same, zero or 1, does not matter. Sure there is some background noise, but the probability of data corruption due to wrong 0 from 1 recognition is practically nonexistent.

You have to pump some data through your FSB bus to make it constantly switching from 0 to 1 and vice versa to trigger the error, and for this you have to load your CPU with some job. More to this, to increase the probability of error, you have to run several processes simultaniosly and make them share common memory or anyway exchange data.

[JumpingJack]

THANK YOU JumpingJack !
thats why eye read these forums good info....

I am by no means a bussing expert ... however, I have spent a bit of time reading up on this some time ago... quite embarrassingly actually. When the UltraDMA 100 HDs starting showing up I bought one, when installing it I simply grabbed the closest cable, a 20 pin 20 wire cable.

When I started it up, and measured the throughput, it ran at 33 ... scratched my head, forgot about it, then went back and rebuilt the computer... this time I grabbed the 20 pin / 40 wire cable (I should correct above, the 40 pin is actual a 2 conductor 40 line cable) ... wolla ... duh.

I was curious as to why this was the case.... I pretty much spilled my guts on all that I know.

David Kanter is much more knowedgable on this topic, he wrote a great bussing tech article here:
http://www.realworldtech.com/page.cf...WT082807020032 (CSI)
http://www.realworldtech.com/page.cf...1303183140&p=1 (Bus basics)

Jack

[JumpingJack]

I don't understand why are you insisting on the obvious and at the same time denies obvious.
In hypotetical absolute idle state (which is never happening in reality) you have your GTL voltage level always the same, zero or 1, does not matter. Sure there is some background noise, but the probability of data corruption due to wrong 0 from 1 recognition is practically nonexistent.
You have to pump some data through your FSB bus to make it constantly switching from 0 to 1 and vice versa to trigger the error, and for this you have to load your CPU with some job. More to this, to increase the probability of error, you have to run several processes simultaniosly and make them share common memory or anyway exchange data.

The bus master will actuate the bus to keep status on the bus agents... sitting with the CPU does not mean activity is not occuring on the bus... just not much of it.

This errata is relating to a physical problem with the signalling, not a logical one... hence, software does not need to be running in order for the bus to be interrupted. That is all that I am saying... meaning, a small but finite probability exists that a marginal voltage on the bus will cause a hiccup.

Your bolded statement is false.

jack

[Cronos]

(Is it odd that Prime 95 crashes and doesnt give an error? I had that happen 3 times, expecting a certain error (such as a rounding one etc)

Well, thats because not every error leads to rounding error, and there are so many possible errors that no single test programm can possibly trigger them all. What is worse, there is often no way to even detect every triggered error.

[Cronos]

The bus master will actuate the bus to keep status on the bus agents... sitting with the CPU does not mean activity is not occuring on the bus... just not much of it.

Status is set/monitored by some constant levels, not switching. Only activity initiated by some agents leads to bus switching activity.

Anyway, this is not really important as absolute idle bus state is never happening.

[JumpingJack]

Status is set/monitored by some constant levels, not switching. Only activity initiated by some agents leads to bus switching activity.

Anyway, this is not really important as absolute idle bus state is never happening.

Ok. ok... you're right, I am wrong... I learned something new. Thanks.

Cheers
Jack

[btdvox]

Well, thats because not every error leads to rounding error, and there are so many possible errors that no single test programm can possibly trigger them all. What is worse, there is often no way to even detect every triggered error.

I just meant to say that Rounding is one of them, I have had many errors in the past with prime and orthos :P haha

anyways my last 3 questions for you guys and im done with the subject as talking about it makes me more anxious for no reason lol:

1) Do we know that the Xbit labs article is talking directly about the errata?
2) If there is such a error dont you think we would be seeing people talk about it other than this one errata, I have searched alot of the main sites i visit and not one hiccup about these chips other than some people put 1.6 volts in them and fried it. Litteraly i have not seen one about this error or that could be this error...
3) Im not use to reading these documents really, but people above stated there usually for a certain spec of people and this one in example was done only in the labs and not with any software... in the errata it self it states there is no fix and all there doing is creating a new revision so that it would work with lower end mobos so to state- will this fix the problem? lol I guess what im also asking not just for me but for everyone; What FSB speed would be too high? I see alot of review sites using 333 and 400 ( Anandtech uses 400 FSB on there qx9650 review with there x38)

Ok and lastly before you all are bored with my comments, it states any C0 yorkies- Isnt QX9770 a C0 yorkfield- according to toms hardware it is and it uses a 1600 FSB...
It looks like the errata was probably talking about older Motherboards and the VRM not being able to push out enough juice- leading to the FSB having failures not being able to push all the data through. (gtlref)

[HDCHOPPER]

thanks for the links JumpingJack

[JumpingJack]

I just meant to say that Rounding is one of them, I have had many errors in the past with prime and orthos :P haha

anyways my last 3 questions for you guys and im done with the subject as talking about it makes me more anxious for no reason lol:

1) Do we know that the Xbit labs article is talking directly about the errata?
2) If there is such a error dont you think we would be seeing people talk about it other than this one errata, I have searched alot of the main sites i visit and not one hiccup about these chips other than some people put 1.6 volts in them and fried it. Literally i have not seen one about this error or that could be this error...
3) Im not use to reading these documents really, but people above stated there usually for a certain spec of people and this one in example was done only in the labs and not with any software... in the errata it self it states there is no fix and all there doing is creating a new revision so that it would work with lower end mobos so to state- will this fix the problem? lol I guess what im also asking not just for me but for everyone; What FSB speed would be too high? I see alot of review sites using 333 and 400 ( Anandtech uses 400 FSB on there qx9650 review with there x38)

Ok and lastly before you all are bored with my comments, it states any C0 yorkies- Isnt QX9770 a C0 yorkfield- according to toms hardware it is and it uses a 1600 FSB...
It looks like the errata was probably talking about older Motherboards and the VRM not being able to push out enough juice- leading to the FSB having failures not being able to push all the data through. (gtlref)

1) No, I am inferring ... based upon the timing of the publication of the article and the appearance of the errata. Of all the rumors, several popped up why Intel pushed out the mainstream quads, this one makes the most sense.

2) Errata are always over-blown, people hear the word 'mistake' or 'defective' and the assume the worse. Intel stated in the errata report they have not observed it on any software... the AMD TLB errata was way overblown as well, all CPUs have errata .. AMD's K8 has something like 157 (some fixed some not), C2D has 90 or over 100 (have not counted in a while), this CPU (the 9650) has something like 67 and more will turn up no doubt. This does not make the CPU defective.... it simply means that under highly specific situations a very specific bit pattern can turn on an error, most errors are trapped by the MCA corrected and/or are benign, in some cases they can be fixed with a BIOS update and some microcode. Cronos is just trying to scare you.

These chips OC like a bat out of hades --- Cronos again was misrepresenting the data above... and they are achieving remarkable results:
http://www.anandtech.com/cpuchipsets...oc.aspx?i=3184 (probably the most thorough on the net)
http://www.legitreviews.com/article/583/11/ (4 Ghz/ 400 FSB stable)
http://www.techspot.com/review/75-in...650/page6.html (4 GHz / 400 FSB stable)
http://www.ocworkbench.com/2007/inte...-QX9650/b6.htm (4 GHz / 445 FSB stable)

3) Kinda see my response above, when AMD or Intel prepare a new CPU for launch they under go a battery of tests, which are very thorough ... in fact, there is a whole field of study dedicated to sort, test and validation of these type of devices, you can be very sure that when each company is ready to stamp their name on it then it has been thoroughly put through the ringer. Once launched though, this does not stop them from testing and analyzing the CPUs and as they discover the highly specific test cases, then they publish the errata ... when they do discover a problem, they estimate the probability that the errata could occur ... if they feel it is necessary they will fix it in a new stepping but that does not necessarily mean that the existing product is bad.... it is sorta like software, you may use MS Excel and discover a bug... does that mean MS recalls Excel?? or you can't use Excel.. of course not, you just know not to do that particular series of things again to avoid the bug.


Errata should not bother you, in fact, I always look for errata and check them often, many times giving good info on things that help me understand what the heck is going on (for example, AMD just - finally - updated their errata, and 319 now helps me make sense of my temps).... Errata are simple obscure problems, some more severe than others, but for the most part should not be weighed into a panic mode.

Jack

[JumpingJack]

thanks for the links JumpingJack

You are welcome.

[btdvox]

^^ JumpingJack thanks alot for your knowledge-
It seems the Xbit article is talking about of the issues on that errata specifically- And it would make sense for them to delay there mainstream chips so they work with older mobos. But As the article stated- Why would anyone buy a $1000 QX9650 and have an old mobo that technically was stated not to work with Yorkies in the first place lol.
Anyways makes sense- And yeah i did alot of research b4 i bought the chip and about 10 review sites got AMAZING OC' and all of them stated they did 15-24 hr testing, even new motherboard reviews usually use QX9650 and test them with it.

I can be one to go along with it as I have mine at 4.2 (400X10.5) and it runs like a dream, in fact funny enough i have the exact same temps as Anandtech (68 @ load.)

I know alot of these things get blown out of proportion because some people want to make it seem worse then it is- But I didnt know there were so many erratas! haha.
The thread should state more specficially all yorkies have instability problems with older 4 layer PCB mobos lol and if your pushing out 475-500 FSB (which would have instability issues anyways as these chips dont go that high as seen from reviewers....)

Thanks again jumpingjack. Im now 8 hr prime stable on Blend and Small fft-

[-iceblade^]

ha ha... at least AMD are honest about their flaws...

[btdvox]

ha ha... at least AMD are honest about their flaws...

Youd be a fool to think AMD's PR is any different than Intels.

All companies run the same- they want one thing only- your money.

[OBR]

from good source i know, this problem is not fixed in C1 revison ...

[BenchZowner]

from good source i know, this problem is not fixed in C1 revison ...

Problem is... I've never faced this issue, and every single guy that I know with a QX9650/QX9770 has yet to face this issue.

I'm not bothered at all.

[camouflage]

I'm happy with mine - sometimes the C0 rev. shows the "low voltage bug" :

[tenax]

well, if there's truly a quad bug that can cause major disfunction, my ES 9450 with a B1 stepping (only B1 i've seen) should have been hit with it i'd think. i've seen enough data on the 9450 and the xeon equivalent now to say that aside from the fact my sensors are all locked, i can overclock my fsb as much as the next guy without errors. (and running 24/7 stable since i built my system in early january.)