All C0 Yorkfields have potential instability problem, confirmed by Intel

[Cronos]

From the last "Intel® Core™2 Extreme Processor QX9650 and Intel® Core™2 Quad Processor Q9000 Series Specification Update"
http://www.intel.com/design/processo...pdt/318727.htm

Errata AV51

AV51. Front Side Bus GTLREF Margin Results Are Reduced for Die-to-Die
Data Transfers in Intel® Core™2 Extreme Processor QX9650, Which
Can Lead to Unpredictable System Behavior

Problem: In a synthetic testing environment, Intel has observed that some processor, chipset, and motherboard configurations may experience reduced Front Side Bus (FSB) voltage margin during some certain die-to-die data transfers. This combination of configurations and data transfers is rare. This lower voltage margin could lead to FSB data bit errors, which can lead to unpredictable system behavior.

Implication: When this erratum occurs, it leads to FSB marginality in the system during processor die-to-die transactions, which can lead to unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.


Fixed in C1.

I'd say, pretty good chance this errata can be triggered in Linpack 64b, though i have not tested it myself.

[Warboy]

ouch

[emoners]

guess waiting for the new quads will take longer than i thought ....

[JumpingJack]

From the last "Intel® Core™2 Extreme Processor QX9650 and Intel® Core™2 Quad Processor Q9000 Series Specification Update"
http://www.intel.com/design/processo...pdt/318727.htm

Errata AV51

AV51. Front Side Bus GTLREF Margin Results Are Reduced for Die-to-Die
Data Transfers in Intel® Core™2 Extreme Processor QX9650, Which
Can Lead to Unpredictable System Behavior

Problem: In a synthetic testing environment, Intel has observed that some processor, chipset, and motherboard configurations may experience reduced Front Side Bus (FSB) voltage margin during some certain die-to-die data transfers. This combination of configurations and data transfers is rare. This lower voltage margin could lead to FSB data bit errors, which can lead to unpredictable system behavior.

Implication: When this erratum occurs, it leads to FSB marginality in the system during processor die-to-die transactions, which can lead to unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.


Fixed in C1.

I'd say, pretty good chance this errata can be triggered in Linpack 64b, though i have not tested it myself.

Unlikely, this is a signaling problem within the package. http://download.intel.com/design/pro...s/31872602.pdf, GTLRef sets the reference level for the common signals on the FSB, as such if the GTLRef is marginal (i.e. not enough voltage -- it is a differential signal bus), then the die to die communciations can be disrupted. Intel's specs for the signal is +/- 0.1 volts depending on whether it is high or low... if a this voltage is marginal, the errata states that core to core comms can be interrupted.

Stressing the CPU with software does not trigger this.... pumping up bus speed and the associated voltage drop may ... i.e. if the board vendors do not give enough supply voltage, then the signal die to die can be a problem and would trigger the problem.

In my opinion, it would appear that Xbit had this original december rumor right:
http://www.xbitlabs.com/news/mainboa...rocessors.html

I serious doubt if you put this CPU into a high quality board you would see a problem ... at least that is my interpretation of the errata.

[Cronos]

Stressing the CPU with software does not trigger this.... pumping up bus speed and the associated voltage drop may ... i.e. if the board vendors do not give enough supply voltage, then the signal die to die can be a problem and would trigger the problem.

You HAVE TO stress CPU with software to trigger the error. But you are right, the higher the FSB, the more likely this will happen. In fact, this may be one of the causes for relatively low FSB wall on many Yorkfields.

Lets wait for mass availability of newer C1 stepping, all Q9450/Q9550 are supposed to be based on C1. Another strong reason not to buy now super expensive QX9650.

[hersounds]

sorry but what about wolfdale ? have bugs too? only the temp?

[Leeghoofd]

Could this be that one of my QX9650 needs more juice at stock speed then the other to be stable, really 1.19 volts for 3ghz is really crap... it clocks up nicely to 4ghz at 1.38 but at stock it really worries me... Vid is the same for both 1.125...

[antari]

I'd say, pretty good chance this errata can be triggered in Linpack 64b, though i have not tested it myself.

Do you ever not talk about Linpack 64-bit?

[Cronos]

Do you ever not talk about Linpack 64-bit?

I'll stop as soon as everyone start using it I am selfish here - the more people will routinely use Linpack, the more reliable information i
will have.

[MarlboroMan]

sorry but what about wolfdale ? have bugs too? only the temp?

no, its a bug between the core dies link. Wolfdales are single die, so there is no bug at all... (some high temps thou..)
Thats why Intel are NOT selling cheap quad-cores and a limited amount of X Edition.
On March 3 we will start to see some ES C-1 stepping chips benches...

The question is:
Will it be overclock monster? like when Q6600 series changed B-3 to G-0

The QX9650 C-0 stepping have some kind of low FSB wall, thats why you always see extreme benches with high multi and low fsb...

Description of Change to the Customer:

Reason for Revision: Correct the post conversion MM number
The Boxed Intel® Core™2 Extreme Processor QX9650 will undergo the following changes for the
C-0 to C-1 stepping conversion:
- New SSPEC and MM numbers for the converting product
- CPUID will change from: 0x00010676 to: 0x00010677
- C-0 package is pin compatible with C-1 package
- There are no changes to Electrical, Mechanical and Thermal processor Specifications.
- Intel anticipates no changes to customer platforms designed to Intel guidelines.


Customer Impact of Change and Recommended Action:

There are no feature set changes between the C-0 and C-1 steppings.
The Intel® Core™2 Extreme Processor QX9650 C-1 stepping will require motherboard
manufacturers to update their BIOS to support the new C-1 processor stepping. Minimal re-
qualification and/or validation is expected for the stepping conversion. Processor engineering
samples will be made available to channel motherboard manufacturers prior to general customer
availability to facilitate BIOS updates and validation activities.

QX9650 3 GHZ C-0 BX80569QX9650 S LAN3 894493 C-1 BX80569QX9650 S LAWN 897412

[jonny_ftm]

This is all intel dirty marketting.
The rumors of Intel yorkfield delayed because of bugs were revealed early december by anonymous intel internal sources, just when AMD revealed the bug in their quadcore CPUs. AMD, released enough data on the errata for motherboard manufactures to implement a bios workaround. That workaround caused a great loss of performance, and contributed to the "death" of AMD. AMD, at least, were fair and honest. Also their bug appeared in only very rare circumstances.

Now Intel: they immeadiately OFFICIALLY denied any bug targetting the QX9650 CPUs and claimed the delays in yorkfields were due to the delay in X48 chipset and because of their roadmap. They firmly denied any bug affecting the QX9650. As a result, the QX9650 stocks were sold at unbelievable prices, their credit increased, while AMD was pushed to the abyssal zone.

Now, they come and claim: hey, we discovered a bug in the QX9650, but of course, we won't call them back.

The looser: customer
The winner: the rich intel. Sadely, customers are too poor to call them in justice. They would for sure loose the verdict

That's what happen when no more competition is on the market. Intel already did that with pentium (do you recall?), and now, they don't hesitate to do it again...

[JumpingJack]

You HAVE TO stress CPU with software to trigger the error. But you are right, the higher the FSB, the more likely this will happen. In fact, this may be one of the causes for relatively low FSB wall on many Yorkfields.

Lets wait for mass availability of newer C1 stepping, all Q9450/Q9550 are supposed to be based on C1. Another strong reason not to buy now super expensive QX9650.

In this 'bug', not really ... it is not a logical error, it is a physical error. Certainly, if you stress with software the chance will increase, but this is a marginality in the signalling within the package ... it could happen just sitting there.

[C'DaleRider]

OOooooooooo, the sky is falling....let's go hang Intel for lying.

Of course, what everyone is missing is that this erratum was documented by Intel on Dec. 20, 2007, so this is NOTHING NEW!!!! Then again, why not get outraged today by something that's been known for almost two months....and has been public for as long.

As for the "rumor" that was linked, if one spends $1000 on a cpu, why in the heck would one then cheap out and buy a 4-layered PCB motherboard, an admittedly cheaper motherboard, vs. a higher quality built 6-layered PCB motherboard? That's what I gleaned from the "rumor", that the cheaper built mb's have some signal noise problems with cheaper built motherboards:

"...issues with quad-core code-named Yorkfield processors occur on affordable mainboards that utilize 4-layer print-circuit boards (PCBs) and do not affect expensive platforms that are based on 6-layer PCBs."

"Since many mainboards based on Intel P35 chipset that are based on 4-layer PCB are already available and are utilized by large system vendors.... As a result, Intel has decided to slightly alter its chips so that they could work in existing infrastructure..."

I notice nowhere mentioned is any problem with X38/X48 based motherboards in that rumor....only P35 mbs.....

So, cry the sky is falling........cause it ain't. It's only hysterical anti-Intel fanbois crying about nothing new.........

[Mav451]

Regarding the 4 vs. 6 layer, since my DFI board is 6 layer, then the problem shouldn't occur, even though I'm on P35 (not x38) right?

*actually this is all moot, if I buy a C1 anyway haha.

[jonny_ftm]

OOooooooooo, the sky is falling....let's go hang Intel for lying.

Of course, what everyone is missing is that this erratum was documented by Intel on Dec. 20, 2007, so this is NOTHING NEW!!!! Then again, why not get outraged today by something that's been known for almost two months....and has been public for as long.

As for the "rumor" that was linked, if one spends $1000 on a cpu, why in the heck would one then cheap out and buy a 4-layered PCB motherboard, an admittedly cheaper motherboard, vs. a higher quality built 6-layered PCB motherboard? That's what I gleaned from the "rumor", that the cheaper built mb's have some signal noise problems with cheaper built motherboards:

"...issues with quad-core code-named Yorkfield processors occur on affordable mainboards that utilize 4-layer print-circuit boards (PCBs) and do not affect expensive platforms that are based on 6-layer PCBs."

"Since many mainboards based on Intel P35 chipset that are based on 4-layer PCB are already available and are utilized by large system vendors.... As a result, Intel has decided to slightly alter its chips so that they could work in existing infrastructure..."

I notice nowhere mentioned is any problem with X38/X48 based motherboards in that rumor....only P35 mbs.....

So, cry the sky is falling........cause it ain't. It's only hysterical anti-Intel fanbois crying about nothing new.........

Didn't see where you got your sources for affected motherboards based on PCB layers
It doesn't figure on intel errata sheets

Also, intel are just like any manufacture: when there's no competition, they put them selves in an abuser situation. And why the hell they didn't offcially announce it in december? Well, just to sell their chips as most would have waited for new revisions, dot

[celemine1Gig]

The real question, instead of moaning and whining about how bad Intel is, should be:

Who has already encountered that stability issue at stock speed?

If you can name more poeple than your fingers can count, then it would perhaps remotely seem to be a real problem. Think about it.

Do you really believe they would still be selling these CPUs if they had serious stability issues?

[JumpingJack]

The real question, instead of moaning and whining about how bad Intel is, should be:

Who has already encountered that stability issue at stock speed?

If you can name more poeple than your fingers can count, then it would perhaps remotely seem to be a real problem. Think about it.

Do you really believe they would still be selling these CPUs if they had serious stability issues?

Quite true, errata are always taken out of context by those who do not understand what they mean....

Intel has not observed this erratum with any commercially available software.

Essentially, they created it in the lab under specific conditions and cannot observe it using any commercial software...... it is a marginality in the package, if the board gives it enough voltage it will never be observed.

If you have a QX9650, just have a high quality board, sell any of that ECS junk.

[btdvox]

K Most the stuff said here confused the crap out of me lol.
I have a QX 9650. It says C0 on CPUZ. I have it running on my EVGA 780i. I run it at 400 FSB ( 1600QDR). I dont think this is a "extreme high" fsb but its more than than the 333 stock fsb.

Will I encounter any of these issues? What are the issues anyways- i never got GTL refs and just left the volts to auto for GTLrefs.

Anyone who could shed some light on this would be much apprciated Im kinda worried now after spending 1K

btw when i search 780i - i see that the reference xfx motherboard is 6 layer PCB- so i am assuming the EVGA which is suppose to be identical is also 6 layer?

[Cronos]

This errata has two implications.

First, the probability of error showing itself is considerably higher on low-end boards than on high-end ones.

And second, even on high-end board we can expect reduced FSB oc potential
from all C0 stepping Yorkfields, which in fact is supported so far by experimental data.

The possible good news for all those who are waiting for more affordable Q9450/9550, is that we can expect C1 stepping to be better FSB clocker. But this is only speculation for now, only the practice will tell.

Higher FSB is especially important for those who want to fully realize all DDR3 potential, as having fast DDR3 with slow FSB is totally pointless.

[mrcape]

Low multis for the new, affordable quads is such a bummer, especially if they can't do 500+ fsb comfortably.

[btdvox]

This errata has two implications.

First, the probability of error showing itself is considerably higher on low-end boards than on high-end ones.

And second, even on high-end board we can expect reduced FSB oc potential
from all C0 stepping Yorkfields, which in fact is supported so far by experimental data.

The possible good news for all those who are waiting for more affordable Q9450/9550, is that we can expect C1 stepping to be better FSB clocker. But this is only speculation for now, only the practice will tell.

Higher FSB is especially important for those who want to fully realize all DDR3 potential, as having fast DDR3 with slow FSB is totally pointless.

Couple of questions:
I still dont get what the error is. Is it the fact that it wont have a high FSB potential because of the FSB voltage problem?
What are these errors and would you know if you got one as in your Computer keeps rebooting or BSODs etc. ?

Secondly I dont see anywhere stating that it only has to deal with 4 Layer PCB's. Sorry to ask these questions but I think I am in the clear. Im only using DDR2 which a higher fsb would always be nice but im sticking with my 400 FSB. Which i dont consider to be very high as ive been using this setting for the last year and a half on my MB's.

Secondly If someone could show where it states it only affects 4 Layer pcbs that would be great, As that would rule me out pretty much ( as stated above dont care too much about achieving higher than a 400 fsb) as I have a 780i and seeing as the 680i was a 6 layer PCB i can only assume that the 780i is also LOL.

Funny thing is this errata has been out since dec 20th. but its the first im seeing of this- and it states many places that its only in experimental situations theyve seen this- Im assuming if my Chip was having issues i wouldnt be able to have it Prime95 stable for 8 hrs on both blend and Small FFT (Which is what i use to "test" for stability and have passed) ..

Thanks for any help in advance!

[Cronos]

Couple of questions:
I still dont get what the error is. Is it the fact that it wont have a high FSB potential because of the FSB voltage problem?
What are these errors and would you know if you got one as in your Computer keeps rebooting or BSODs etc. ?

The margin in voltage level between GTL low and high states is too low in C0, which may lead, for certain FSB transactions, to CPU not properly recognizing 0 from 1 in data stream. As a result, data corruption may occur.
This may be greatly aggravated by the low-quality noisy PCB on some cheap boards and by FSB overclocking even on high-quality motherboards.

Actual manifestation will not necessary lead to any "eye" visible errors, as most errors are not visible and only most severe and rare ones lead to bluescreens/hangs.

[JumpingJack]

K Most the stuff said here confused the crap out of me lol.
I have a QX 9650. It says C0 on CPUZ. I have it running on my EVGA 780i. I run it at 400 FSB ( 1600QDR). I dont think this is a "extreme high" fsb but its more than than the 333 stock fsb.

Will I encounter any of these issues? What are the issues anyways- i never got GTL refs and just left the volts to auto for GTLrefs.

Anyone who could shed some light on this would be much apprciated Im kinda worried now after spending 1K

btw when i search 780i - i see that the reference xfx motherboard is 6 layer PCB- so i am assuming the EVGA which is suppose to be identical is also 6 layer?

Actually, you could do us all a favor and run prime95 for 48 hours and let us know... The errata is not entirely clear, the xbit article seems to suggest the lower end 4 layer PCBs can cause the problem.

However, I doubt you will see anything... it has been produced in the lab, and all the 9650 reviews, even the overclocking reviews, all claim stability even for the 4+ GHz OCs.

Errata, as mentioned above, are almost always over blown. Don't take that as they don't exist, but just because an errata entry exists does not mean that you will lock up ever day.

[JumpingJack]

Couple of questions:
I still dont get what the error is. Is it the fact that it wont have a high FSB potential because of the FSB voltage problem?
What are these errors and would you know if you got one as in your Computer keeps rebooting or BSODs etc. ?

Secondly I dont see anywhere stating that it only has to deal with 4 Layer PCB's. Sorry to ask these questions but I think I am in the clear. Im only using DDR2 which a higher fsb would always be nice but im sticking with my 400 FSB. Which i dont consider to be very high as ive been using this setting for the last year and a half on my MB's.

Secondly If someone could show where it states it only affects 4 Layer pcbs that would be great, As that would rule me out pretty much ( as stated above dont care too much about achieving higher than a 400 fsb) as I have a 780i and seeing as the 680i was a 6 layer PCB i can only assume that the 780i is also LOL.

Funny thing is this errata has been out since dec 20th. but its the first im seeing of this- and it states many places that its only in experimental situations theyve seen this- Im assuming if my Chip was having issues i wouldnt be able to have it Prime95 stable for 8 hrs on both blend and Small FFT (Which is what i use to "test" for stability and have passed) ..

Thanks for any help in advance!

So here is the story ... a rumor broke out end of november/beginning of december that Intel was delaying their quad launch. People speculated, there are wild rumors all over the net. Here is the Xbit article: http://xbitlabs.com/news/mainboards/...rocessors.html

Here is another speculations:
http://www.engadget.com/2007/12/19/i...mds-struggles/

Several stories were written, Xbitlabs has a unique story explaining that Intel discovered that if the FSB signal is marginal then the processor could lock up on lower quality boards, typically 4 layer PCB (el cheapo boards).

This makes sense... if the errata were a logic problem, then dual cores should suffer too, but for quad cores, there are two bus agents sharing the bus, think of it like you and your wife each using a hair dryer, run one hair dryer fine, but run them together .. pull down too much and trip a breaker. The extra core on the die adds an extra load to the bus, this will create a voltage drop... if the board does not have the margin for that voltage drop, then the voltages will not be enough to generate the appropriate differential to GTLref.

Your board is not in this class, you have no worries. You are getting worried over nothing. Question, does it boot? Have you run software on it?

Also, Intel publishes on a fixed monthly schedule... if any new errata are found, they will appear on the website under technical documents and specification updates: http://www.intel.com/design/processo...pdt/318727.htm

If a new revision is created, it will be posted per the following 2008 schedule: January 16, February 13, March 12, April 16, May 14, June 11, July 16, August 13, September 10, October 15, November 12, December 10

You probably had not heard of it because the Inquirer has not picked up on the update yet.

Jack

[btdvox]

Sounds way to finicky too me, Seems like its just a bunch of PR vs PR making statements because they found something and tried to test for a fault and found one in prob the most odd situation.
Anyways I can already tell you that i am running the Chip on my 780i @ 400 FSB and have already primed for a day. I have also overclocked and prime95'd for 8 hours on both blend and small fft.

To tell you the truth it was the most pleasurable and easy OC I have ever done. Pretty much because i knew what i wanted my 24/7 target to be and what volts i should try to input. Im stable on my 780i which has bad vdroop for any chip. Im running my FSB volt @ 1.4 and my CPU @ 1.475 (1.42 when idle in windows and 1.368 when under load) And have had no issues, i first tried at 1.45 but got a prime95 crash and then upped the voltage and am now stable.
I have almost the same results as AnandTech does on there website with the QX9650 and have really heard NOTHING bad ever about this chip (in fact read any of the reviews ive read about 10-15 and you'll see everyone raved about this Chip and how it overclocks) until this errata (which does sound like a certain spec' systems are having issues with. They ran there 9650 @ 4.2 GHZ with a watercool setup (which i am too PA 120.2 and dtek fuzion) and got temps of 68 at load- (Mine loads at 67 lol)


Data corruption occuring is something you can usually spot and know- And the errors are usually caught by windows or a dskcheck if its on the Harddrive,

So the fact that some of you are saying "you prob wont even know its happening" and there is a fault is very very unlikely and no offense if no one knows its happening and everything is working ok- It prob means everything is Ok.

Im not the only one with this Chip and someone stated they prob made a limited run- If you check X38 or 780i boards you'll see ALOT of people with QX9650's its not really limited... And of course alot of others have G0 Q6600s.