QX9650 changes VID at higher Mhz......!!!

[camouflage]

Nice find here, my QX usually has a VID of 1.1375 but at higher speeds it turns to 0.9875:







I think 0.9875 is closer to real cause this chip runs 4GHz prime at 1.208 volts and 4Ghz 32M at 1.200 volts:





Somebody ever heard of a chip changing its VID ???

[NightRaven]

now this is interesting... gonna check mine too

either way. GODLIKE 9650 agaiN!

[camouflage]

now this is interesting... gonna check mine too

either way. GODLIKE 9650 agaiN!

Keep us updated if You notice the same....................

[billdavis]

yeah same here

i also noticed it on my last q6600

[camouflage]

yeah same here

i also noticed it on my last q6600

That's interesting - so it is no special QX9650 issue........, maybe something only happens to quads?

Someone here noticed this with a dual core?

[ziddey]

vid changing is a part of c1e. although it should switch up vs down from idle to load. My e6400 exhibits this as well. Although motherboards handle vid changes differently once you start overclocking. Some kill it off altogether. Some have the voltage still able to scale down at idle, but dont register any vid changes in coretemp (and I imagine other programs).

For instance, I take advantage of c1e on my e6400. I can't remember if it worked on the p5b or not, but it has on the dfi p965 as well as abit ip35. At load, it'd be just shy of 1.5v. But at idle, it'd stay around 1.3 or so. Brings down idle, and hopefully gives some more longevity

[NightRaven]

i think most overclockers off c1e or eist totally when overclocking.. so i assumed that it would not be so..

[Z3R0-CooL]

same thing happens to mine.. i suspect coreTemp error.. but hey.. maybe it happens.

[Falkentyne]

Um.....how come my VID is .7125v ? ......
That isn't normal for a QX9650, is it?

And my chip does 3.8 @ 1.2875v and 4 ghz @ 1.375v quad prime, but doesn't that seem ...um....not right for that type of VID?
Or is it because i'm running it in a P5wdh and a newer board might do this with less vcore?

[ziddey]

vid may not be read properly at the moment. but that low a vid would be reasonable for the lower multipliers.

[crazyea]

The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 2-3 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 2-4 and Figure 2-1as measured across the VCC_SENSE and VSS_SENSE lands.

This may have something to do with it. I dunno.

For more info read: Intel QX9650 White paper, page 14.

http://www.intel.com/design/processo...hts/318726.htm