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Thread: FINALLY! Barcelona(s) + Asus L1N64......

  1. #26
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    Quote Originally Posted by kyosen View Post
    HT Link multiplier
    Target registers are F0x[0E8,0C8,0A8,088].
    Barcelona/K10 is designed to have 4 HT Link,
    but it looks that one of them is disabled for current K10 Opteron...
    ...in this case, F0x0E8 is reserved for 4th HT Link, and it's disabled now.
    Then, we can observe the value like 80750660 on F0x[0C8,0A8,088] with MchbarEdit.
    From AMD's BIOS and Kernel Developer's Guide, Page 146,
    HT Link is set as below:
    80750660 = x5
    80750560 = x4
    80750460 = x3
    80750360 = reserved (...probably x2.5!? not tested)
    80750260 = x2
    80750160 = reservied (...probably x1.5!? not tested)
    80750060 = x1
    We can write desirable value on it, and after rebooting, it should be changed.
    # Also we should be able to change HT Link width 8bit/16bit with registers mod
    # for F0x[0C4,0A4,084] in similar way, but I've not tested it.
    Just to add more information.. with 2 processor install there are 2 Register address need to be set up for both processor to change the HT Link Clock. Which are:

    Processor node 0 = Bus#0 Device#24 Function#0 (For processor number 1)
    Offset 88h (32bit access mode) LDT Link 0
    Offset A8h (32bit access mode) LDT Link 1
    Offset C8h (32bit access mode) LDT Link 2
    Offset E8h (32bit access mode) LDT Link 3

    Processor node 1 = Bus#0 Device#25 Function#0 (For Processor Number 2)
    Offset 88h (32bit access mode) LDT Link 0
    Offset A8h (32bit access mode) LDT Link 1
    Offset C8h (32bit access mode) LDT Link 2
    Offset E8h (32bit access mode) LDT Link 3


    Here is some guide from me with WPCREdit:
    http://www.xtremesystems.org/forums/...&postcount=554

    After changing.. REBOOT is required to invoke LDTSTOP_L function and change actual HT-Link
    Last edited by tictac; 11-07-2007 at 07:29 PM.

  2. #27
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    Quote Originally Posted by kyosen View Post
    North Bridge multiplier
    Target register is F3x0D4.
    We can observe the value like C331F024 on F3x0D4 with MchbarEdit,
    and last digit (4 in the above case) is NbFid, i.e. NorthBridge Frequency ID.
    NB clock is defined as "200 x (NbFid + 4) / (2^NbDid)"
    NbDid, i.e. NorthBridge Divisor ID is defined at MSRC001_00[68:64], and it's 0 in default.
    2^0=1, so we can think simply NB clock = 200 x (NbFid + 4).
    We need to reboot to give effect to changing F3x0D4[NbFid].
    # Oppositely, NbDid is changeable without reboot, so the system can reduce NB clock dynamically.
    Additional information to access it with WPCEDIT

    With 2 processor there are 2 register need to be edit :-

    1) Processor node 0 = Bus#0 Device#24 Function#3 (For processor number 1)
    Offset D4h (32bit access mode) , Bit 0,1,2,3,4 (5bit)

    2) Processor node 1 = Bus#0 Device#25 Function#3 (For processor number 2)
    Offset D4h (32bit access mode) , Bit 0,1,2,3,4 (5bit)

    NB clock = 200 x (NbFid + 4).
    *NBFid = in decimal


    Bit = Hex = Decimal = NB Speed calculation
    00001b = 1h = 1 = NB clock 200x (1+4) = 1000MHz
    00010b = 2h = 2 = NB clock 200x (2+4) = 1200MHz
    00011b = 3h = 3 = NB clock 200x (3+4) = 1400MHz
    00100b = 4h = 4 = NB clock 200x (4+4) = 1600MHz
    00101b = 5h = 5 = NB clock 200x (5+4) = 1800MHz
    00111b = 6h = 6 = NB clock 200x (6+4) = 2000MHz
    ....
    11011 = 1Bh = 27 = NB clock 200x (27+4) = 6200MHz

    Last edited by tictac; 11-25-2007 at 03:14 PM. Reason: COrrection on device id

  3. #28
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    Lol 6200 Mhz Nb

  4. #29
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    Quote Originally Posted by tictac View Post
    Additional information to access it with WPCEDIT

    With 2 processor there are 2 register need to be edit :-

    1) Processor node 0 = Bus#0 Device#24 Function#3 (For processor number 1)
    Offset D4h (32bit access mode) , Bit 0,1,2,3,4 (5bit)

    2) Processor node 1 = Bus#0 Device#24 Function#3 (For processor number 2)
    Offset D4h (32bit access mode) , Bit 0,1,2,3,4 (5bit)

    NB clock = 200 x (NbFid + 4).
    *NBFid = in decimal


    Bit = Hex = Decimal = NB Speed calculation
    00001b = 1h = 1 = NB clock 200x (1+4) = 1000MHz
    00010b = 2h = 2 = NB clock 200x (2+4) = 1200MHz
    00011b = 3h = 3 = NB clock 200x (3+4) = 1400MHz
    00100b = 4h = 4 = NB clock 200x (4+4) = 1600MHz
    00101b = 5h = 5 = NB clock 200x (5+4) = 1800MHz
    00111b = 6h = 6 = NB clock 200x (6+4) = 2000MHz
    ....
    11011 = 1Bh = 27 = NB clock 200x (27+4) = 6200MHz

    Thanks for this info tictac
    I wanted to ask you if you know anyone who was able to run Barcelona/Phenom (be it retail or ES) with NB clock greater than 2GHz?Since according to your posting,the chips are able to run the IMC/L3(both inside the NB domain) at a far greater frequencies(6.4Ghz,in theory) of those 1.6/1.8Ghz we saw in tests up to now...
    I suspect the ~2.5Ghz NB clock could greatly help reduce the L3 latency as well as mem. latency!And we know AMD uses the same sram for L2 and L3 and we know they are able to clock them as high as 3.2Ghz on 6400+ case and as up to 2.7 revG2(and presumably the 2.9Ghz as yet unreleased G2 part will work at).Since the L2 in these K8s is the same type of cache AMD used for the L3 in K10,there should be no reason this L3 couldn't work on ~2.5Ghz-like clocks.
    Last edited by informal; 11-09-2007 at 08:26 AM.

  5. #30
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    Quote Originally Posted by SP33DFR34K View Post
    Lol 6200 Mhz Nb
    Maximum NBFid = 27 + 4 = 31 x 200 = 6200MHz but...doh....

    NB Fid must not exceed MaxNBFid (located on CPU_MSRC001_0071, bit 63-59) if we set it higher no change will be set

    Quote Originally Posted by informal View Post
    Thanks for this info tictac
    I wanted to ask you if you know anyone who was able to run Barcelona/Phenom (be it retail or ES) with NB clock greater than 2GHz?Since according to your posting,the chips are able to run the IMC/L3(both inside the NB domain) at a far greater frequencies(6.4Ghz,in theory) of those 1.6/1.8Ghz we saw in tests up to now...
    I suspect the ~2.5Ghz NB clock could greatly help reduce the L3 latency as well as mem. latency!And we know AMD uses the same sram for L2 and L3 and we know they are able to clock them as high as 3.2Ghz on 6400+ case and as up to 2.7 revG2(and presumably the 2.9Ghz as yet unreleased G2 part will work at).Since the L2 in these K8s is the same type of cache AMD used for the L3 in K10,there should be no reason this L3 couldn't work on ~2.5Ghz-like clocks.
    i havent seen anybody run it higher than NB multiplier of 9.
    Last edited by tictac; 11-09-2007 at 08:32 AM.

  6. #31
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    NB clock is crippled in non split-voltage boards. The idea is that this is initialized by the BIOS through an undocumented WR-MSR that informs the processor to go in this mode. Disassembly should provide the location and values involved.
    AMD stated that they did it that way to prevent boards going the way of the dodo because of overvoltage/amperage; and I don't believe that. So... yah... when this barcelona goodness comes to the KFN5D be it one way or the other I've got some plans for that part.

    On another note : To my knowledge MaxFID cannot be overridden with the Opteron.
    Last edited by twobombs; 11-10-2007 at 12:58 AM.

  7. #32
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    2.6G with Vcore mod

    I connected wire from ADP3186 Pin#8 FB to GND with 50k-ohm VR.
    http://www.oohashi.jp/c-board/file/L..._Vcore-mod.jpg

    I could reach 2.6G@1.36V with water-cooling(no air-conditioner assisted).

    SuperPI1M:
    http://www.oohashi.jp/c-board/file/L..._NB-x8_3-4.png

    CineBench10:
    http://www.oohashi.jp/c-board/file/C...K10B1-2.6G.png

    I noticed that ClockGen-1.0.5.3 is also available,
    but anyway I must change clock step by step, 1 click by 1 click,
    and L1N64-SLI is not robust to clock changing...
    ...it mostly cause freeze/blue-screen/reboot before reaching 220MHz

  8. #33
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    Kyosen-chan: the older AMD power monitor shows the speed during overclock correct and works better with p-states on non-split voltage boards. The new one is full of those bugs.

    Powerfull OCL, good Bench.

  9. #34
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    Does Socket F support Split Power Planes or there will be an updated Socket F?
    (maybe SocketF+)
    IQ_NOT_LESS_OR_EQUAL

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  10. #35
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    The big issue here seems to be it's not possible to raise the CPU clock generator frequency above 200 MHz with this board due to BIOS limitations. So, why not build an external circuit or generator to replace the onboard signal to the CPU, instead of relying on the board's PLL hardware? This technique has worked well for me in the overclocking of numerous video game consoles and would likely be applicable to x86 hardware as well.

    Generators exist to produce a squarewave of the required amplitude at any frequency, and so do lower-cost solutions like VCOs and fixed-frequency crystal oscillators. You'd just need to sever the clock trace to the CPU and attach your own signal. I don't imagine this would be a problem since the CPU reference frequency seems to be arbitrary and distinct from that of any other component on most overclocker-friendly boards (in the pursuit of separating FSB, PCI, AGP, PCI-Express, and other buses so a rising frequency on one won't interfere with proper operation of the rest.)

  11. #36
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    Quote Originally Posted by Epicenter View Post
    Generators exist to produce a squarewave of the required amplitude at any frequency, and so do lower-cost solutions like VCOs and fixed-frequency crystal oscillators. You'd just need to sever the clock trace to the CPU and attach your own signal. I don't imagine this would be a problem since the CPU reference frequency seems to be arbitrary and distinct from that of any other component on most overclocker-friendly boards (in the pursuit of separating FSB, PCI, AGP, PCI-Express, and other buses so a rising frequency on one won't interfere with proper operation of the rest.)
    I don't think it's independent, (related to multi of the same frequency)
    Then, in order to lock the pll of the cpu, there is probably a sequence starting in the "catch" (not sure of the english term) of the cpu's pll and going at a certain speed up to the fsb value.

  12. #37
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    The KFN5/32 had that System Clock limitation, I reverse engineered the timer chip inside the MCP55/Nforce3600 chipset logic and this made it possible to overclock the timer chip to previously thought impossible speeds. I think the same can be done with the L1N64, I haven't had this board in my hands to check if there is a timer chip. The KFN has none, chances are that the L1N64 hasn't got one either; the chipset upscales from a 14.something Mhz X-tal.

    CPU-z verification
    Last edited by twobombs; 11-10-2007 at 09:51 AM.

  13. #38
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    Quote Originally Posted by Sunfire View Post
    Does Socket F support Split Power Planes or there will be an updated Socket F?
    (maybe SocketF+)
    It's all called Socket F

  14. #39
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    Quote Originally Posted by nemrod View Post
    I don't think it's independent, (related to multi of the same frequency)
    Then, in order to lock the pll of the cpu, there is probably a sequence starting in the "catch" (not sure of the english term) of the cpu's pll and going at a certain speed up to the fsb value.
    Two things; #1 I'm pretty sure it'd work since the PLL shouldn't NEED to lock, but you'd need to hold the frequency stable wherever you are generating it.. and #2 I'm not so sure there's really a PLL at all, and the CPU isn't just being fed a multiplied value from a crystal on the board. Example; the CPU clock generator frequency on my AM2 board isn't that stable; it drifts by ~+/-3 MHz. That's pretty substantial. Something more robust might be in place on a high end server board like this, but who knows.

    Here's another idea; to maintain synchronization why not build a simple circuit to multiply the system crystal frequency up to the desired speed and feed that to the CPU, set multiplier and you should be good to go.

  15. #40
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    Quote Originally Posted by Epicenter View Post
    I'm not so sure there's really a PLL at all, and the CPU isn't just being fed a multiplied value from a crystal on the board.
    I believe it's inside the cpu and that the multiplier is something like a /N in the feedback loop.
    3GHz or even 5 or 6GHz (ln2 for example) is quite high on a board.

    Quote Originally Posted by Epicenter View Post
    Here's another idea; to maintain synchronization why not build a simple circuit to multiply the system crystal frequency up to the desired speed and feed that to the CPU, set multiplier and you should be good to go.
    It's probably far better. (but with classical PLL design you will have integer multi, if the cpu work (x2) with a 300MHz input your board is only at 150MHz, and the memory too, so clock of memory should probably be x2)
    Last edited by nemrod; 11-11-2007 at 12:11 AM.

  16. #41
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    The System Clock is fed to the CPU sockets and a lot of other places in a lot of forms. Do not underestimate the time critical factor of the System Clock during POST, in power saving, regular and overclocking scenarios. I've done a big piece on it here ( and that's part of 3 months' worth of work ) P-states and System Clock changes have very time-critical elements, especially in systems that are already POST-ed. That's the main reason why Clock Gen crashes on a whole bunch of new Socket F boards; The MCP55 interface of ClockGen is faulty because of the change from one setting to another causing lockups. I've found a way around that problem, and thats also in that thread.
    Last edited by twobombs; 11-11-2007 at 12:45 AM.

  17. #42
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    Quote Originally Posted by Sunfire View Post
    Does Socket F support Split Power Planes or there will be an updated Socket F?
    (maybe SocketF+)
    Quote Originally Posted by twobombs View Post
    It's all called Socket F
    It is called Socket F with "Dual Dynamic Power Management"(DDPM):

    http://www.amd.com/us-en/0,,3715_12353,00.html
    http://www.amd.com/us-en/Corporate/V...120221,00.html

    For simplicity's sake we should call it Socket F+. DDPM it is just a separate, more complicate marketing name for the server segment. It is the same game as PowerNow! / Cool&Quiet.

    cheers

    Opteron146

  18. #43
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    Quote Originally Posted by twobombs View Post
    The System Clock is fed to the CPU sockets and a lot of other places in a lot of forms. Do not underestimate the time critical factor of the System Clock during POST, in power saving, regular and overclocking scenarios. I've done a big piece on it here ( and that's part of 3 months' worth of work ) P-states and System Clock changes have very time-critical elements, especially in systems that are already POST-ed. That's the main reason why Clock Gen crashes on a whole bunch of new Socket F boards; The MCP55 interface of ClockGen is faulty because of the change from one setting to another causing lockups. I've found a way around that problem, and thats also in that thread.
    Interresting reading (not yet finished)

    This part let me think I was right with "Then, in order to lock the pll of the cpu, there is probably a sequence starting in the "catch" (not sure of the english term) of the cpu's pll and going at a certain speed up to the fsb value.":

    It gets worse actually; a big change in the clock timer of the the MCP55 *always* causes a total system crash; like the P-states in the AMD processor this has to be done in relative small incremental steps. This has to do with the latency of the gates and the system in general that in which a too big increase in the System clock would be like throwing a big stone in a pond, disturbing the system. Small increments. I found out that those increments actually had to be bitwise, hence the 4h increments, causing only a relative minor change at once through writing to one byte at the time, but a value that is not too high and could still be digested by the system.
    In fact, for pll stuff, there is a catch region (frequency region related to the free running and the filter of the pll) where the pll is always look if a frequency in that region is in entry then, there is a wider region where pll could stay look if move not to quick (in order, to have the new frequency - the old frequency below the cut-off of the filter, the maximum speed of change is related to some "boring" pll stability analysis)

    From what I understand you're able to set higher fsb by changing slowly value (windows) but you can't yet start with high speed in bios? This is probably related to the speed of the change.
    Last edited by nemrod; 11-11-2007 at 07:58 AM.

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    The reason is that I haven't found a good place where I can change the values that are written into the MCP55 is that I've seen several places where the system starts in a very early state, but the FSB selection routine is written in high-level 'C' and when it is compiled a sort of 'housekeeper' runs through the list of 'things-to-do and to clean up' and calls routines accordingly. At that point in time the system isn't initialized as it is after POST and much more flexible settings/timings are allowed. ( I haven't seen an array with the FSB/Clock variables either )

    This 'housekeeper' that I've called it is a complicated and elaborate piece of machinecode and to prevent getting stuck into that area because of time constraints I ran through the early stages of the POST and found out that the System Clock is setup by a hidden SMBus. RW Everything showed it was the SMBus @ 2800h ( 3 registers at 2808h/2809h/280Ah ) after POST, and that's where the manipulation of the registers started. A datasheet of a known AMD clockdriver and an experiment with my notebook later the work was done.

    A side effect, and another confirmation, of the software overclock you can't soft reboot because the system will want to revert to its default (in BIOS) and freezes. To reset you'll need to press the reset button twice. Once to get it into default speed, and the second time to actually boot at the default speed. The housekeeper knows how to handle this though when its set in the BIOS, but the BIOS only allow a 5% OCL. Manuals and some small RW-Everything files here [ we're getting offtopic here ? ]
    Last edited by twobombs; 11-11-2007 at 08:37 AM.

  20. #45
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    Could somebody post some nominal & OCL 'Octo' Barcelona L1N64 Sisoft Sandra Bandwith and CPU/FPU goodness here ?
    That would be great, tnx.
    Last edited by twobombs; 11-11-2007 at 09:33 AM.

  21. #46
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    Quote Originally Posted by Epicenter View Post
    Two things; #1 I'm pretty sure it'd work since the PLL shouldn't NEED to lock, but you'd need to hold the frequency stable wherever you are generating it.. and #2 I'm not so sure there's really a PLL at all, and the CPU isn't just being fed a multiplied value from a crystal on the board.
    AFAI last checked, there's a PLL within the CPUs and there's also one on the motherboard - both are checked by the BIOS upon bootup and have to return values in sync of each other or your system won't boot (or rarely it will but with very erratic behavior). Sometimes the northbridge also has a PLL.
    Example; the CPU clock generator frequency on my AM2 board isn't that stable; it drifts by ~+/-3 MHz. That's pretty substantial. Something more robust might be in place on a high end server board like this, but who knows.
    Check the Base Timer value in SiSoftware Sandra after running a benchmark. It should be 3.6MHz very consistent and stable and that's what you need to see if your PLL/s are working correctly. If you had fluctuations in that, your clock frequencies would be very unstable (at least in the desktop range) and wrong.

    There shouldn't be any fluctuations in the clock generators, they are usually extremely accurate, and if there is that'll affect the Windows time, RDTSC and system frequency based clock readings (such as many benchmarks). I 'aint sure about server systems though.

  22. #47
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    I think he meant the cpu clock was fluctuating by ~3mhz which is a bit much but pretty normal... 3mhz pll fluctuation is a lot.
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    Hello, Sisoft, barcelona, anyone ?

  24. #49
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    I dont think sisoft works correctly with barcelona..
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    All along the watchtower the watchmen watch the eternal return.
    Want to use my Anti-asus logo? Go ahead, but use this link please!: http://i853.photobucket.com/albums/a...sus/noasus.gif
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    Here is a Cpu-z screenshot from a retail cpu.
    Attached Images Attached Images

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