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Thread: FINALLY! Barcelona(s) + Asus L1N64......

  1. #1
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    FINALLY! Barcelona(s) + Asus L1N64......

    Here's a cut and paste from my post in the VIP section here @ XS:

    *Please don't PM me for the bios. I have to first get permission since it's not my property *


    Good news:



    Bad new:

    1. Bios seems to clear itself every time I change the memory config. I was going to start testing for a bad stick/slot, but then I got tired of setting every bios option after swapping out each stick

    2. I either have a bad stick, a bad slot, or this bios doesn't like to boot with 4x2gb of DDR2. It will boot fine with 3x2gb, but not 4.

    3. The board now takes an unusually long time to boot. From what I can tell from the post codes from my debug card, the board does some sort of "cycle" when rebooting. I'll check the codes later....

    4. Although there are options for voltage and overclocking the FSB in bios, I can safely say that the FSB option DOES NOT WORK. I can set a certain FSB in bios, but the board just ends up booting @ default (200mhz). If I go back into bios, my OC'd setting is STILL there, but doesn't actually do anything. Maybe it has something to do with the fact that there's a page in the bios which indicates that the cpu frequency is unchangeable - I'm figuring that there's some sort of lock on the bios still.

    5. The quads seem to be running a bit slower clock-for-clock than in my Tyan s3993. So far, Spi and Cinebench scores are both worse on the L1N64.

    That's about it for now. I'm just glad we've mad some progress. Now to unlocking those bios options BTW, I thought you guys may get a kick outta this screeny. This is what the older version of CPUZ detected my cpu's as:



    lol...Octal Phenom

  2. #2
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    octal phenom..? wow..

  3. #3
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    Nice Steven finally

    If anyone wants the BIOS is OK PM me or Steven.

  4. #4
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    Very Cool
    ʇɐɥʇ ǝʞıl pɐǝɥ ɹnoʎ ƃuıuɹnʇ ǝq ʇ,uop

  5. #5
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    Quote Originally Posted by metro.cl View Post
    Nice Steven finally

    If anyone wants the BIOS is OK PM me or Steven.
    Let's just make it easy for everyone and have metro.cl be the one to PM lol...

    BTW...thanks!

  6. #6
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    Now the fun really begins.

  7. #7
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    w0000t! Now to see how it compares to the qx9650. And just so that amd finally will win a benchmark, let's disable a few cores on the qx9650:p

    While this is nice, being realistic, where is it actually applicable?
    Quote Originally Posted by Hans de Vries View Post

    JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    .....}
    until (interrupt by Movieman)


    Regards, Hans

  8. #8
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    whats the ram timings? 1-3-3-3??????

  9. #9
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    w00t wr for ram
    Quote Originally Posted by Hans de Vries View Post

    JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    .....}
    until (interrupt by Movieman)


    Regards, Hans

  10. #10
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    interesting, cpuz doesn't display the l3 cache. I thought only the b0s had the l3 disabled, or do also the b1s then (which by the way, where are the BAs? those should have been out by now)?
    Quote Originally Posted by Hans de Vries View Post

    JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    terrace215 post: IPC decreases, The more I post the more it decreases.
    .....}
    until (interrupt by Movieman)


    Regards, Hans

  11. #11
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    Quote Originally Posted by AliG View Post
    interesting, cpuz doesn't display the l3 cache. I thought only the b0s had the l3 disabled, or do also the b1s then (which by the way, where are the BAs? those should have been out by now)?
    I think that pic is the old one with old version cpuz..
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  12. #12
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    these are great news! except for the memory bug... :P and the OC ones.

    Can you tell us Steve how much slower is L1N64 compared to the Tyan one?

    Moreover: how are the "bugs" with ccNUMA and memory clocks??????

  13. #13
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    4.5 mb of cache ... mmmm 6.5 mb for the 1mb l2 versions? ( 64*4 + 64*4 + 512*4 + 2048 and 64*4 + 64*4 +1024*4 +2048 ? )
    mobo: msi 970 g46
    gpu: amd 6870 core 1ghz/ mem 1140 arctic twin turbo (6850 coming soon for franken-fire)
    cpu: 955be @ 3.8ghz @ 1.375v's 2.6ghz n/b 1.275 scythe scrt-1000
    ram: 2x2gb samsung hyko @ 800mhz @ 6-8-8-24
    psu: corsair 650hx
    hdd's: 500gb + 1tb ( 16 and 32mb cache ) samsung

    mobo: biostar r690a-m2t
    gpu: E4690 @ 725core/750mem
    cpu: 4200+ @ 3ghz 1.43 hyper 212 evo
    ram: (random) 2x512mb 2x1gb @ 375 5-5-5-15
    psu: blue storm II 500w
    hdd's: 850gb total

  14. #14
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    Will there be a 1mb l2 version?

  15. #15
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    Finally!

    Still 2 weeks before official Phenom launch !

    Post some scores and try to clock FSB from Windows
    RiG1: Ryzen 7 1700 @4.0GHz 1.39V, Asus X370 Prime, G.Skill RipJaws 2x8GB 3200MHz CL14 Samsung B-die, TuL Vega 56 Stock, Samsung SS805 100GB SLC SDD (OS Drive) + 512GB Evo 850 SSD (2nd OS Drive) + 3TB Seagate + 1TB Seagate, BeQuiet PowerZone 1000W

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  16. #16
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    Quote Originally Posted by s7e9h3n View Post
    Let's just make it easy for everyone and have metro.cl be the one to PM lol...

    BTW...thanks!
    Ok i will help metro

    If metro didnt reply you can get it here:
    http://www.esnips.com/doc/68f16563-2...64-SLI-WS-0301

  17. #17
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    I received the BIOS from metro.cl, many thanks!!!
    And now, my L1N64-SLI has booted up with s7e9h3n's 2350(B1)

    L1N64-SLI has no support for DDPM/split power plane,
    so there is no NorthBridge voltage display on AMD Power Monitor,
    and NorthBidge is running at x8 multiplier
    http://www.oohashi.jp/c-board/file/L...NB-1.6_400.png

    I could change NB multiplier x8 -> x9, with modifying register and reboot.
    http://www.oohashi.jp/c-board/file/L...NB-1.8_400.png

    ClockGen 1.0.4.6 is available for L1N64-SLI, but I feel that the response is
    a bit slower than KFSN4-DRE's case.
    At first, I couldn't reach FSB230 with x3 HT Link multiplier,
    but I noticed that HT Links are set as x3, x3, x1.
    http://www.oohashi.jp/c-board/file/L...T_x3_x3_x1.png

    So I changed HT Link multiplier as x3, x3, x3, and reboot.
    http://www.oohashi.jp/c-board/file/L...T_x3_x3_x3.png

    Finally I got 2.5G
    http://www.oohashi.jp/c-board/file/L..._NB-x8_3-5.png

    Now, sleeeeepy...good night
    ---------
    Kyosen

  18. #18
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    hei its 4am here in bali.. you spend all night playing with this toys.. hehe.. nice.. keep em coming.. thx for sharing with us

  19. #19
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    Am i wrong or is that a nice boost?
    39sek 2000Mhz / 400Mhz 5-5-5-15-21 vs. 32sek 2500Mhz / 417MHz 5-5-5-15-21

    SPI depends on ram, yes? So 7 sek boost on 17MHz isnet that pretty good, or did i get it all wrong?
    Last edited by nullface; 11-07-2007 at 10:48 AM.

  20. #20
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    Quote Originally Posted by kyosen View Post
    I received the BIOS from metro.cl, many thanks!!!
    And now, my L1N64-SLI has booted up with s7e9h3n's 2350(B1)

    L1N64-SLI has no support for DDPM/split power plane,
    so there is no NorthBridge voltage display on AMD Power Monitor,
    and NorthBidge is running at x8 multiplier
    http://www.oohashi.jp/c-board/file/L...NB-1.6_400.png

    I could change NB multiplier x8 -> x9, with modifying register and reboot.
    http://www.oohashi.jp/c-board/file/L...NB-1.8_400.png

    ClockGen 1.0.4.6 is available for L1N64-SLI, but I feel that the response is
    a bit slower than KFSN4-DRE's case.
    At first, I couldn't reach FSB230 with x3 HT Link multiplier,
    but I noticed that HT Links are set as x3, x3, x1.
    http://www.oohashi.jp/c-board/file/L...T_x3_x3_x1.png

    So I changed HT Link multiplier as x3, x3, x3, and reboot.
    http://www.oohashi.jp/c-board/file/L...T_x3_x3_x3.png

    Finally I got 2.5G
    http://www.oohashi.jp/c-board/file/L..._NB-x8_3-5.png

    Now, sleeeeepy...good night
    Kyosen-san, are you running a single 2gb stick of memory?

  21. #21
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    If you have issues you can send me feedback an i will help get a better bios.

    Send me the problemas and rig specs.

    Regards

    p.d. there are specific instructions to flash the bios dont do it the normal way or you might kill something

  22. #22
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    Quote Originally Posted by nullface View Post
    Am i wrong or is that a nice boost?
    39sek 2000Mhz / 400Mhz 5-5-5-15-21 vs. 32sek 2500Mhz / 417MHz 5-5-5-15-21

    SPI depends on ram, yes? So 7 sek boost on 17MHz isnet that pretty good, or did i get it all wrong?
    You've probably miss the most important factor

    (39x2/2.5=31.2)

  23. #23
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    Quote Originally Posted by s7e9h3n View Post
    Kyosen-san, are you running a single 2gb stick of memory?
    No, I'm running my board with 1GB Reg. memory modules.
    I tried 2x 2350 and 4x = 2x + 2x memory modules in this morinng.
    My 1GB modules is 1 rank(bank) type, so it looks that bank-interleave is disabled,
    but all 4x modules are detected and working:
    http://www.oohashi.jp/images/L1N64_K10_x2_memory_x4.png

    And here, additional explanation of register mod with MchbarEdit...
    ...instead of private mail...it's convinient, I think

    HT Link multiplier
    Target registers are F0x[0E8,0C8,0A8,088].
    Barcelona/K10 is designed to have 4 HT Link,
    but it looks that one of them is disabled for current K10 Opteron...
    ...in this case, F0x0E8 is reserved for 4th HT Link, and it's disabled now.
    Then, we can observe the value like 80750660 on F0x[0C8,0A8,088] with MchbarEdit.
    From AMD's BIOS and Kernel Developer's Guide, Page 146,
    HT Link is set as below:
    80750660 = x5
    80750560 = x4
    80750460 = x3
    80750360 = reserved (...probably x2.5!? not tested)
    80750260 = x2
    80750160 = reservied (...probably x1.5!? not tested)
    80750060 = x1
    We can write desirable value on it, and after rebooting, it should be changed.
    # Also we should be able to change HT Link width 8bit/16bit with registers mod
    # for F0x[0C4,0A4,084] in similar way, but I've not tested it.

    North Bridge multiplier
    Target register is F3x0D4.
    We can observe the value like C331F024 on F3x0D4 with MchbarEdit,
    and last digit (4 in the above case) is NbFid, i.e. NorthBridge Frequency ID.
    NB clock is defined as "200 x (NbFid + 4) / (2^NbDid)"
    NbDid, i.e. NorthBridge Divisor ID is defined at MSRC001_00[68:64], and it's 0 in default.
    2^0=1, so we can think simply NB clock = 200 x (NbFid + 4).
    We need to reboot to give effect to changing F3x0D4[NbFid].
    # Oppositely, NbDid is changeable without reboot, so the system can reduce NB clock dynamically.

  24. #24
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    could someone please confirm or deny if there is still problems with barcellonas and CCNUMA and/or dual-channel?

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    show us sisoft sandra memory benchmark for NUMA validation..

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