AMD to start 45nm ramp in H1 2008

[grunge100]

Phildoc,

Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.

[PhilDoc]

I know its about 45nm, but SOI is part of the equations and how they do with 65nm is also part of it. The 3.7G is real just look at the AMD forum and you can read all about it.

Here just to save you some time. http://valid.x86-secret.com/show_oc.php?id=253783

[grunge100]

[Shintai]

Phildoc,

Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.

And compared to competitors it is what?

SOI today is a big bleeding wound on AMD. It was the chance they took. Bulk vs SOI is an easy question for 45nm and down. At 130nm and 90nm it was another ballgame.

I personally dont like AMDs work with IBM on this area. IBM tends to go exotic rather than practical in many cases. And there just aint room for that with a fierce competition. Specially not when you are also with your head down in the mud.

[savantu]

Phildoc,

Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.

Those 2 things aren't exclusive.

Individual OCs say virtually nothing about what AMD can crank out of the 65nm process.

AMD's 65nm process was optimized for low power , not speed.As a result 65nm K8 isn't able to match 90nm K8 in top frequency , at least not yet( probably never will ) .

As a rule of thumb a shrink is able to do 20% better than the previous process size at the same power.

3-3.2GHz 90nm 125w -> 3.6-3.8GHz 65nm 125w

AMD is stuck at under 2.8GHz.

See more here :

Interestingly, this first application of 65-nm technology was designed not to improve performance over the previous, 90-nm Athlon, but to reduce power consumption.

http://www.eetimes.com/showArticle.j...leID=196701745

The tradeoffs involved in keeping leakage under control = slow transistors speed , difficult to reach higher frequencies.

Dirk Meyer says something interesting :

The issue has been simply one of tuning the design to the technology so as to support a high volume ramp.

IMO , they cover the flaws of the process with the design of the chip , as to minimize them. ( same as Thoroughbred days , they added more layers , etc )

K10 has excellent power usage when running at low speed , once you crank up the speed the power usage goes through the rough ( slower , thicker transistors need more voltage , remember the 1.52V 2.5GHz sample ? ).

[bedlamite]

Hmm.
Are CPU transistors realy so different from GPU ones?
New Radeons 38x0 will be 55 nm.
Isnt it at least a bit simmilar?

[Hornet331]

gpus arnt produced by amd fabs, they are produced by TSMC or UMC, which use a different tech.

[informal]

Those 2 things aren't exclusive.

Individual OCs say virtually nothing about what AMD can crank out of the 65nm process.

AMD's 65nm process was optimized for low power , not speed.As a result 65nm K8 isn't able to match 90nm K8 in top frequency , at least not yet( probably never will ) .

As a rule of thumb a shrink is able to do 20% better than the previous process size at the same power.

3-3.2GHz 90nm 125w -> 3.6-3.8GHz 65nm 125w

AMD is stuck at under 2.8GHz.

See more here :

http://www.eetimes.com/showArticle.j...leID=196701745

The tradeoffs involved in keeping leakage under control = slow transistors speed , difficult to reach higher frequencies.

Dirk Meyer says something interesting :

IMO , they cover the flaws of the process with the design of the chip , as to minimize them. ( same as Thoroughbred days , they added more layers , etc )

K10 has excellent power usage when running at low speed , once you crank up the speed the power usage goes through the rough ( slower , thicker transistors need more voltage , remember the 1.52V 2.5GHz sample ? ).

Savantu,you can't expect that uarchitecture that was originally designed for 90nm process and introed at 130nm to scale up to 3.6-3.8Ghz at 65nm.It isn't only the process that matters,but as D.Mayer recently said (about K10),"wedding the design to the process".
So no,nobody ever expected K8(in X2 variant even less!) to go to 3.6-3.8Ghz ,125W on 65nm process.There are other limitations in K8 that would come into play,it's not the process alone.

[Shintai]

Hmm.
Are CPU transistors realy so different from GPU ones?
New Radeons 38x0 will be 55 nm.
Isnt it at least a bit simmilar?

The process is much different. CPUs require a much higher quality process, more metal layers and so on. I dont even think TSMC would be able to make a standard 65nm K8/K10 or Core/Core2.

55nm is also just an optical shrink of 65nm and mainly a cost improvement.

[perkam]

55nm is also just an optical shrink of 65nm and mainly a cost improvement.

Which they pass on to customers thankfully There are also some architecture improvements Shintai, be they as insignificant as you wish, the addition of UVD, DX10.1 and SM4.1 are big marketing cues that AMD will use to their advantage.

Perkam

[Shintai]

Which they pass on to customers thankfully

Perkam

Thats kinda funny.

The firm turned in net profits of NT$30.37 billion on revenue of NT$88.96 billion for its third quarter, which ended the 30th of September last. That gave TSMC a gross margin of 45.8 per cent and a net margin of 34.1 per cent.

They sure keep their share...and abit more

And for those comparing it with Intel/AMD. Remember there is no chip R&D needed. And their fab volume is quite bigger.

[informal]

The better the process is, the higher the CPU frequencies are.

I agree about the designing part. K8 was never designed to clock high, but it was evolving during the time and was changed in each stepping. With every new revision AMD have redesigned parts of K8's logic to reduce the cumulative stage delay, which also resulted in higher frequency. It wasn't only the processes which brought K8 to clocks above 3GHz, but also the logic redesigning.

Even AMD's 45nm isn't any faster then their 65nm, they still can redesign some parts of the 65nm K10 logic. That would result in higher clocked 45nm K10's and/or reduced power consumption, compared to 65nm.

Yes,but those weren't as radical changes as pipeline changes would be(even K10 hasn't changed much in that respect) .AMD were sticking to the original plan and as you said,tweaked the design to the smaller node when it was possible to net further clock/power benefit.

[savantu]

Savantu,you can't expect that uarchitecture that was originally designed for 90nm process and introed at 130nm to scale up to 3.6-3.8Ghz at 65nm.It isn't only the process that matters,but as D.Mayer recently said (about K10),"wedding the design to the process".
So no,nobody ever expected K8(in X2 variant even less!) to go to 3.6-3.8Ghz ,125W on 65nm process.There are other limitations in K8 that would come into play,it's not the process alone.

I'm fully aware of that , however ,as ceteris paribus a shrink will offer some frequency gains.
I'm really interested to see what frequency will K10 reach since its pipeline is basically the same as K8.The sudden jump in power consumption from 2.3/2.4GHz to 2.5/2.6GHz is indicative of an inflexion point in the shmoo.

[savantu]

Even if K10's pipeline length and configuration is same as K8's, the K10 stages are more complex. That means more cumulative latency in some of the stages, which causes the CPU to clock lower. K10 also has a much more complex northbridge, new level of cache, two more complex memory controllers. All this might be preventing K10 to clock higher. If this is the case AMD will need to redesign some of these things in order to boost the CPU frequency. Also, the redesigning of such parts may reduce latencies and improve frequencies of the L3 and the northbridge, which will result in better per clock performance.

Bingo!

[SEA]

Even if K10's pipeline length and configuration is same as K8's, the K10 stages are more complex. That means more cumulative latency in some of the stages, which causes the CPU to clock lower. K10 also has a much more complex northbridge, new level of cache, two more complex memory controllers. All this might be preventing K10 to clock higher. If this is the case AMD will need to redesign some of these things in order to boost the CPU frequency. Also, the redesigning of such parts may reduce latencies and improve frequencies of the L3 and the northbridge, which will result in better per clock performance.

Agree

... But there is absolutelly nothing new: it is constant process, when next revision is faster then previous: 90nm F2 > F3, 65nm G1 > G2
I would say if you dont have years to make one final rev - it is the only way to tune it up eventially - from revision to revision.

[perkam]

Even if K10's pipeline length and configuration is same as K8's, the K10 stages are more complex. That means more cumulative latency in some of the stages, which causes the CPU to clock lower. K10 also has a much more complex northbridge, new level of cache, two more complex memory controllers. All this might be preventing K10 to clock higher. If this is the case AMD will need to redesign some of these things in order to boost the CPU frequency. Also, the redesigning of such parts may reduce latencies and improve frequencies of the L3 and the northbridge, which will result in better per clock performance.

Perhaps, but I said it before, I'll say it again, the B2 Stepping K10s will clock similarly to K8s

Perkam

[Shintai]

Perhaps, but I said it before, I'll say it again, the B2 Stepping K10s will clock similarly to K8s

Perkam

65 or 90nm K8s?

But I dont think so really.

[BrowncoatGR]

Even if K10's pipeline length and configuration is same as K8's, the K10 stages are more complex. That means more cumulative latency in some of the stages, which causes the CPU to clock lower. K10 also has a much more complex northbridge, new level of cache, two more complex memory controllers. All this might be preventing K10 to clock higher. If this is the case AMD will need to redesign some of these things in order to boost the CPU frequency. Also, the redesigning of such parts may reduce latencies and improve frequencies of the L3 and the northbridge, which will result in better per clock performance.

All of this has(or at least should) happen during the design phase not after release. But i guess AMD would work on the design and process after release to improve clockspeed. If their 45nm is really as close as they state i doubt its worth putting any R&D into 65nm though. I'm also waiting to see how much they can gain from the use of SGOI if they get around to implementing it at 65nm after all. A 40% increase in electron mobility is quite a substantial improvement if it's true.

[happychappy]

It's starting to look up for AMD

About time

[savantu]

Perhaps, but I said it before, I'll say it again, the B2 Stepping K10s will clock similarly to K8s

Perkam

Still sure about that ?

http://www.xtremesystems.org/forums/...d.php?t=163780

When you need >1.53V to get to 3GHz while a K8 on 65/90nm does it at under 1.4V , allow me to take your claim with a healthy dose of salt.

[Zytek_Fan]

Still sure about that ?

http://www.xtremesystems.org/forums/...d.php?t=163780

When you need >1.53V to get to 3GHz while a K8 on 65/90nm does it at under 1.4V , allow me to take your claim with a healthy dose of salt.

As I said in that thread, that Phenom looks very suspicious...so don't believe it until it can be confirmed from more than one site

[DeathReborn]

Still sure about that ?

http://www.xtremesystems.org/forums/...d.php?t=163780

When you need >1.53V to get to 3GHz while a K8 on 65/90nm does it at under 1.4V , allow me to take your claim with a healthy dose of salt.

Clock yes, Volt no. I have to go to 1.55v to get 3GHz on my X2 so it's not hugely dissimilar.

[Shintai]

Clock yes, Volt no. I have to go to 1.55v to get 3GHz on my X2 so it's not hugely dissimilar.

OC doesnt count.

[savantu]

As I said in that thread, that Phenom looks very suspicious...so don't believe it until it can be confirmed from more than one site

What's suspicious ?

When Anandtech reviewed the 2.5GHz B2 it ran at 1.52V too , that's stock.
Tell me that's "normal".

[GoThr3k]

was it BA or B2?