Unleashing the Bear(lake): Changing "strap" on the fly

[The Stilt]

I have been working on Bearlake for few weeks now.
I have collected some data that is required to make Memset support Bearlake chipset.

Asus especially has not make my work very easy since their bioses are doing something that they are not supposed to be doing

Anyway Felix has done some excellent work on the program, and it will be released soon.

While I was monitoring the changes in chipset registers I noticed something interesting when the motherboard changed the chipset "strap" (internal latencies).

Usually these latencies cannot be changed unless MCH is fully reseted.
(Or maybe we just didn´t figure out how )

Luckily Bearlake is different and the latency can be changed without resetting the MCH

The "strap" has ten different "stages"
1 is the tightest and 10 is pretty much super loose.
One is almost never used, but the second and third are quite common.

Asus actually uses the slowest possible value when booted at 533FSB, and so does Gigabyte at 417FSB or so.

With 1:1 divider at 533FSB Asus uses slower setting than at the same FSB with 6:5 divider. Both can be tweaked of course.

This feature will be added in Memset at some point.

At the mean time you can look at the results.

I used 5-5-5-9-25-5-8-2-2-5 (tCL-tRCD-tRP-tRAS-tRFC-tWR-tRD-tWTR-tRRD-tRTP) settings and 6:5 divider for Everest.

None of the timings were changed between the tests, just the "strap".

For SuperPI I had to use 1:1 divider because the ram isn´t able to pass SPI32M at DDR1280 with 2.55V. The timings however are identical.

The first test of Everest was run with level 8 setting and the last with level 5 setting.

The first SuperPI run was done at level 10 setting and the last (fastest) at level 6 setting.

See the difference?

Everest Cache & Memory Benchmark

Level 8 (boot value for 533FSB / 6:5 divider)
Click images for larger picture



Level 7



Level 6



Level 5 (tightest possible value at this frequency)



SuperPI 32M

Level 10 (boot value for 533FSB / 1:1 divider)



Level 9



Level 8



Level 7



Level 6 (tightest possible at 533FSB / 1:1)

[Pt1t]

Nice one Roger

[ashley]

awesome !

[^don.k's^]

Hi, nice findings there! I hope you'll be working on the X38 when you can dude!

[Neon Biker]

Great work guys!

PS. Damn, Gigabyte is really playing it safe. The slowest strap from only 417Mhz on? Sheesh.

[cpulloverclock]

Francophony is here

[Learn]

It works also on P965, i discovered that some day ago:
In french:
http://www.ixtremtek.com/forums/showthread.php?t=76

[Pt1t]

It works also on P965, i discovered that some day ago:
In french:
http://www.ixtremtek.com/forums/showthread.php?t=76

I had no more 965p to test

[lowfat]

very nice!

[Lestat]

interesting.

i just wonder how long a chipset can last running at that tight of a strap?


also what was your increase in mch voltage needed ?

i imagine that you needed max volts to hit stage 7 and even quite possibly volt modded??

[Ace-a-Rue]

this is going to be "VERY COOL" to be able to adjust the straps within windows.

[freecableguy]

This is big.

[Lestat]

This is big.

only for bearlake,,, so far.

[Gautam]

965 as well.

[FELIX]

...very great work Roger.
For CR, I just send you an email.

[ineedaname]

WOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOT

Good job
finally something that can change the straps.

When can i dl this???

[The Stilt]

also what was your increase in mch voltage needed ?

i imagine that you needed max volts to hit stage 7 and even quite possibly volt modded??

Well Bearlake happens to be so strong chipset that there is no need for voltage increase

There is no difference in maximum FSB between the different "strap" setting levels.

[eva2000]

interesting for me there was a strap change @500FSB for my Q6600 B3 ES with Asus P5K Deluxe

Q6600 B3 - Asus P5K Deluxe Strap Change

Swapped over to 2x1GB Crucial Ballistix 8500 dual channel kit.

• It seems for my Q6600 B3 max FSB depends on how well memory modules can handle certain settings. Why ? Because my Q6600 B3 can hit 495-500FSB alot easier with this memory than other memory I've tested. Other memory hit max FSB around 490FSB.
• Also I might have found a possible strap change for Asus P5K Deluxe (maybe only noticeable with very very tight subtimings ? ) @500FSB. At 7x500FSB, memtest86+ v1.70 reported 6216MB/s bandwidth. At 7x499FSB, memtest86+ v1.70 reported 6505MB/s bandwidth!.

Super Pi v1.50 32M
7x499FSB = 13m 28.313s
7x500FSB = 13m 37.844s

Everest Ultimate (MB/s)
7x499FSB vs 7x500FSB
Memory Read: 10809 vs 9964
Memory Write: 9096 vs 9115
Memory Copy: 9615 vs 9157
Memory Latency: 46.0ns vs 51.8ns





Settings Used

JumperFree Configuration Settings
AI Overclocking: Manual
CPU Ratio Control: Manual
- Ratio CMOS Setting: 7
FSB Frequency: 499 & 500
PCI-E Frequency: 100
DRAM Frequency: DDR2-1248 & DDR2-1250
DRAM Command Rate: 2T
DRAM Timing Control: Manual
CAS# Latency: 5
RAS# to CAS# Delay: 5
RAS# Precharge: 5
RAS# Activate to Precharge: 9
TWR: 3
TRFC: 30
TWTR: 3
TRRD: 3
TRTP: 8
DRAM Static Read Control: AUTO

Transaction Booster: AUTO
Boost Level: N/A
Clock Over-Charging Mode: AUTO

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

CPU Voltage: 1.5v
CPU Voltage Reference: x0.63
CPU Voltage Damper: Enabled
CPU PLL Voltage: 1.50
DRAM Voltage: 2.40
FSB Termination Voltage: 1.40
North Bridge Voltage: 1.70
North Bridge Voltage Reference: AUTO
South Bridge Voltage: 1.20

Advance CPU Settings
CPU Ratio Control: Manual
- Ratio CMOS Setting: 7
C1E Suppport: Disabled
Max CPUID Value Limit: Disabled
Vanderpool Technology: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
PECI: Disabled

USB Configuration
USB Functions: Enabled
Legacy USB Support: Disabled (need to enable it to detect USB flash drives)

Q6600 B3
7x499FSB
vs
7x500FSB

Strap change does exist it seems at 500FSB changes to lower memory bandwidth performance compared with 499FSB.

[TL1000S]

Great work The Stilt. True legend.
Seems like I "must" have a "bear"-based MB pretty soon.

[ZeroX]

Great finding! thanks for the hard work!

[wtz54321]

Can u guys told us which MCHBar address offset to adjust to strap ?

[dengyong]

Nice work.

[xs64]

post # 321
http://xtremesystems.org/forums/show...143133&page=13

have been working with ASUS the past couple of days here in Taiwan. We should have a beta BIOS in a week or so that will open up memory strap changes on this board plus a couple of other surprises. Running DDR2-1333 at 5-5-6-18 with 2.4V at this time without an issue for one.

Will there be a new Bios for P5K Deluxe that can set strap manually?

[wtz54321]

As far as I know , the strap register is located in FED14C00h register bit 2/1/0 ... And the bit define is 010 = 800 MT/s , 000 = 1066 MT/s , 100 = 1333 MT/s ... And it's not possible to change strap define unless you have a system power off because the strap register is latched only once when the chipset power up in the first time , any system reset will not reset or relatch the strap register ... That's why everytime I change the strap setting , the P5K board shut it down and then power up again to make the new strap working ... If any other register can change the performance , it may be something else , but not the chipset strap setting at all ... Stilt , can u told us which register and what setting to change the performance level ?

[Raja@ASUS]

The latter 965 boards seemed to have this on the fly chipset latency adjustment too, just that nobody made such a big deal at the time...