!!!The Ultimate K8L Thread 2007 & Beyond!!!

[ScythedBlade]

K8L will use intel's SSE4 instructions later anyway ... so it's kinda related. Plus, we like to go bring back reality to some amd fanboys to make them stay normal.

I hope some of you guys get K8Ls soon in like april.

[ether.real]

I may get Barcelona if they have an AM2+ version that supports unbuffered memory. otherwise I will wait for Agena.

[informal]

I may get Barcelona if they have an AM2+ version that supports unbuffered memory. otherwise I will wait for Agena.

There should be one early on,along with the socket F versions.
The price will probably be high in the beginning.

[Fred_Pohl]

Shintai thinks that the whole world should function as intel corp(tm).
Thank God it's not the case.AMD operates in a different manner,and unlike intel they plan their moves carefully and smart,not giving away what they have too early.It's been that way in the past and it will be that way in the future.

Indeed. Like when AMD carefully and smartly hid their last new core (K8) from the public until 4 years before it's launch and the first ES benchmarks didn't hit the web until 16 months before the launch.

[ether.real]

Fred, will you please stop trolling the AMD threads....I barely visit here and I am sick of you already.

[savantu]

Yeah it's a wonder chip,we all know that

You wouldn't notice the obvious even if it struck you in the head...

Really mysterious one

Oh yes , 20% more transistors for SSE4 , who would have thought of that ?
What about improved FP performance or VT2 or the possibility of HT ?

[Fred_Pohl]

Fred, will you please stop trolling the AMD threads....I barely visit here and I am sick of you already.

If you have any relevant facts concerning K8L that you'd like to share, I'd be very happy to hear them. I only visited this thread to learn something about K8L but all I've seen so far is a lot of rumor based speculation, zealous optimism and the fallacious "K8L is ready to go but AMD is keeping it top secret like they always do" argument.

[informal]

You wouldn't notice the obvious even if it struck you in the head...



Oh yes , 20% more transistors for SSE4 , who would have thought of that ?
What about improved FP performance or VT2 or the possibility of HT ?

Just read the realworldtech article ,D. Kanter explained it all pretty well.It's not that hard.HT is a possibility?More like a long shot to me.What improved FP?Minor core revisions don't yield the FP improvement.VT2 is in the line of minor improvement,just like RevF for AMD did bring that one(in pacifica version).
If you base your claims on rumor mill information,you will end up like your smiley.

[Fred_Pohl]

Here's some recent K8L news that may be of interest:

http://www.dailytech.com/article.aspx?newsid=5874

The desktop equivalent of Barcelona, codenamed Agena, is the 65nm flagship of AMD's next-generation desktop processors. Launch frequencies were quoted at "2.4 - 2.6GHz." Previous roadmaps had indicated Agena would debut at 2.7 to 2.9 GHz. Agena will have a 2MB L2 and 2MB L3 cache per CPU. AMD's internal guidance denotes this as a 125W TDP processor. As the flagship, Agena will be the first next-generation desktop launch and is scheduled for Q3'07.

Kuma, the dual-core mainstream next-generation desktop processor was quoted as having launch frequencies of "2.0 - 2.9GHz." Unlike the quad-core Agena processors, Kuma will feature 1MB of L2 and 2MB of shared L3 cache. Kuma will launch with both 89W and 65W TDP variants, but Energy Efficient models scheduled for 35W TDP will follow shortly after.

Rana, the next-generation Sempron successor codename, will launch with frequencies in the 2.1 to 2.3 GHz range. The dual-core CPUs will feature 1MB of total L2 cache, but no L3 cache. Rana's TDP is rated at 65W. Rana will not launch with the Agena flagship; AMD roadmaps have the processor launching at the same time as the Energy Efficient Kuma processors, or approximately Q4'07 if the launch schedule holds together.

[informal]

Here's some recent K8L news that may be of interest:

http://www.dailytech.com/article.aspx?newsid=5874

Good news that semprons are going the way of dual cores with Stars,was about time.

[ether.real]

If you have any relevant facts concerning K8L that you'd like to share, I'd be very happy to hear them. I only visited this thread to learn something about K8L but all I've seen so far is a lot of rumor based speculation, zealous optimism and the fallacious "K8L is ready to go but AMD is keeping it top secret like they always do" argument.

And your trolling is making this thread any better? If you have some relevant facts, share them or shut the hell up.

[Fred_Pohl]

And your trolling is making this thread any better? If you have some relevant facts, share them or shut the hell up.

http://amd-barcelona.com/

At least I'm trying to contribute... how about you?

[GoThr3k]

http://amd-barcelona.com/

At least I'm trying to contribute... how about you?

the day you are contributing something usefull in this thread i will buy you one 1000l of good belgian beer
so thats not going to happen because you are full of BS

[Serge84]

Some people hear should really post under the Intel Section
THIS IS AN AMD THREAD

so stop talking about 6300/4300/6400/Penryn INTEL CRAP
this is a thread about K8L

That was pretty funny.

Here is news from the Analyst Day event in New York today. AMD see the end of the Homogeneous Multicore CPU and the rise of the Heterogeneous Multicore CPU - what they call the Accelerated Processing Unit. This will include not just the usual computing core but several cores dedicated to specialized functions such as graphics, JAVA acceleration, and video encoding/decoding. Having said that, they also said that they are currently working on an 8-core homogeneous multicore CPU.

Fusion will be put on Desktops in this config later after moble units with lesser cores are released. APU's are much more powerful then the CPU's of today and can not be compared.

http://rubyworks.net/forumz/viewtopic.php?t=363

[Fred_Pohl]

the day you are contributing something usefull in this thread i will buy you one 1000l of good belgian beer
so thats not going to happen because you are full of BS

Ummmmmm... I liek Belgian beer! Can my contribution be factually based or must I sing K8L rumors in unison and key with the AMD fanboi choir?

[Plywood99]

Ummmmmm... I liek Belgian beer! Can my contribution be factually based or must I sing K8L rumors in unison and key with the AMD fanboi choir?

Lol, Belgian beer taste too sweaty. How bout a Sam Adam's winter brew...


Ply

[Fred_Pohl]

Lol, Belgian beer taste too sweaty. How bout a Sam Adam's winter brew...


Ply

Sam Adams is another fav but sometimes nothing quenches my thirst like a good Belgian White. Not to mention that 1000L of free Belgian beer is quite an enticing offer.

[Turtle 1]

Yeah it's a wonder chip,we all know that


Really mysterious one

Well you can dismiss the added transitors as NN did. But 1mb of cache more doesn't quit added up to 1 million extra transistor.Its a lot more.

http://techreport.com/etc/2006q4/fall-idf/index.x?pg=1

Here is a quote from this article

The bulk of SSE4's 50 or so instructions is comprised of new compiler vectorization primitives, which should make it easier for compilers to translate software written in high-level languages into effectively parallelized code and data structures. These new instructions encompass both integer and floating-point operations, and include provisions for dual- and quad-word multiplication, blending, and format conversions. SSE4 also has some related "media accelerator" functions that expand SSE's capabilities. Among them are four instructions that round floating-point values to integers and a floating-point dot product capability that should prove especially useful for graphics. Taken together, Intel expects these new instructions to help further the traditional promise of SSE as an accelerator for multimedia, 3D gaming, graphics, and scientific computing.


I doubt very much the the effectively parallelized code means any thing but H/T useing to cores to run 1 thread. Meaning penryn is effectively doubling it performance.

[nn_step]

turtle it is 14.2M transisters per 256kB of Cache :Fact:

[informal]

Well you can dismiss the added transitors as NN did. But 1mb of cache more doesn't quit added up to 1 million extra transistor.Its a lot more.

http://techreport.com/etc/2006q4/fall-idf/index.x?pg=1

Here is a quote from this article

The bulk of SSE4's 50 or so instructions is comprised of new compiler vectorization primitives, which should make it easier for compilers to translate software written in high-level languages into effectively parallelized code and data structures. These new instructions encompass both integer and floating-point operations, and include provisions for dual- and quad-word multiplication, blending, and format conversions. SSE4 also has some related "media accelerator" functions that expand SSE's capabilities. Among them are four instructions that round floating-point values to integers and a floating-point dot product capability that should prove especially useful for graphics. Taken together, Intel expects these new instructions to help further the traditional promise of SSE as an accelerator for multimedia, 3D gaming, graphics, and scientific computing.


I doubt very much the the effectively parallelized code means any thing but H/T useing to cores to run 1 thread. Meaning penryn is effectively doubling it performance.

Wow man,just wow .You sure could help intel marketing dep.

Meaning  penryn is effectively doubling it performance.

QFA( "A" is for arguing ,in the future j/k)

[Turtle 1]

turtle it is 14.2M transisters per 256kB of Cache :Fact:

The cache l1 doesnt matter . penryn uses the same amount of cache L1 . There is 62 million transitors in 1mb of l2 cache x 6 = 372 million transitors in l2 cache. That leaves 38 million transitors of core logic. That means penryn has 5 million less transitors in it for core logic than conroe.. that would mean penryns transitor logic is smaller than conroes. unless the number of transitors it takes to make 1mb cache in conroe is differant than the number of transitors it takes to make 1 mb of cache in penryn which i am sure is the case. That said no one knows how many transitors has been added to the core logic of penryn unless you work at Intel in engineering. FIXED

[savantu]

The cache l1 doesnt matter . penryn uses the same amount of cache L1 . There is 62 million transitors in 1mb of l2 cache x 6 = 372 million transitors in l2 cache. That leaves 38 million transitors of core logic. That means penryn has 5 million less transitors in it for core logic than conroe.. that would mean penryns transitor logic is smaller than conroes. unless the number of transitors it takes to make 1mb cache in conroe is differant than the number of transitors it takes to make 1 mb of cache in penryn which i am sure is the case. That said no one knows how many transitors has been added to the core logic of penryn unless you work at Intel in engineering. FIXED

Umh no...6MB of L2 using 6T cells needs 288 million transistors.Logic,L1+everything else for L2 needs 122 million for Penryn.

Conroe has 4MB of L2 , 192 million transistors.99 million left.

Even if we assume that for each MB of L2 you need 3 million extra transistors , that leaves 104 million for Penryn and 87 for Conroe in logic only.

17 million transistors is 2 P3 cores ( I mean the entire core , with 256KB L2 ) .It is obvious Penryn is much more than a simple shrink.

[pocketbikeuk]

Umh no...6MB of L2 using 6T cells needs 288 million transistors.Logic,L1+everything else for L2 needs 122 million for Penryn.

Conroe has 4MB of L2 , 192 million transistors.99 million left.

Even if we assume that for each MB of L2 you need 3 million extra transistors , that leaves 104 million for Penryn and 87 for Conroe in logic only.

17 million transistors is 2 P3 cores ( I mean the entire core , with 256KB L2 ) .It is obvious Penryn is much more than a simple shrink.

Amazing how amd threads end up about intel if i wanna read about intel il do so in the intel section can people please keep this thread on topic so when some good k8l news is out we dont have to start a new thread as this one is closed.

[MAS]

the second barcelona photo i've ever seen

[nick2crete]

Amazing how amd threads end up about intel if i wanna read about intel il do so in the intel section can people please keep this thread on topic so when some good k8l news is out we dont have to start a new thread as this one is closed.

+1 ..mercy..