K8 65nm (Brisbane) Anandtech Review

[Lightman]

AMD are saying it is for possible larger than 1MB cache later on rather than yeilds. I wonder why they would want very large cache, currently their architecture allows efficient use of small amount of cache, say 512.

Regards

Andy

For me this is just test before Barcelona core. I can bet that L2 cache latency in Barcelona also will be 20Hz.

@ future die shrink of Brisbane:
AMD long time ago stated that first they will use transistor design form 90nm process on 65nm one, then after 3 months from first production samples they will move to native 65nm design (major die shrink, lower voltage, power consumption and hopefully faster switching speed )

[doompc]

AMD must have changed Brisbane's l2 cache latency to improve yelds.
Since it's a 2x512KB die, there is no cache to disable if defective.

K8L might have "normal" L2 cache latency (about 10 cicles, since there won't be an 1MB version).

[gOJDO]

i was under the impression that the FPU was 17, not 15

Yeap, my bad. It is 17 stages.