K8 65nm (Brisbane) Anandtech Review

[zir_blazer]

In-depth Brisbane Review
Anandtech

Anandtech Review gives us some new, unheared of info about K8 65nm:

* Uses the same integer Memory Divisors. This means that the odd Multipliers used for archiving 100 MHz increases can result in even slower Memory Frequency that the even ones.
* Cache L2 Latency increased from 12 clock cycles that all the K8s from initial launch until now had to 20 clock cycles (Remember Prescott to Prescott 2M?). This is the cause for the slighty slower performance on some Benchmarks on the Preview.
* From Anandtech test samples, 65nm Energy Efficient A64X2 4800+ and 5000+ works at 1.35V while the older Windsor 90nm full power A64X2 5000+ works at 1.3V. Smaller manufacturing process but higher Voltage??? However, power consumption is lower anyways, but it should have been better.

It isn't surprising right now that AMD is releasing the DH-F3 and JH-F3 parts that I commented some time ago for their highest end Processors when the 65nm ones scalability AND performance is crippled. AMD, what the hell are you doing?!?!


Source: Anandtech

[gOJDO]

Does this means that AMD have had and still have problems with the 65nm SOI-3 and that the 65nm SOI-3 is slower than the 90nm SOI-2?

That's a bit of a bad typo isnt it?!

Tom

No, it isn't a typo. The latency is measured in cycles, which is same dimension as Hz's.

[zakelwe]

That is strange. If they do move to a "rev B" as LOE hypothesised there will be a move over period where it might be tricky getting the right part.

Currently it seems 90nm AMD is a bargain for us, 65nm is a bargain for AMD!

Regards

Andy

[keiths]

The bulk of the die consists of the l2 cache. Slowing it down would help improve yields. That AMD is using higher voltage than their 90nm parts and that it overclocks poorly also point in the same direction; trouble with their 65nm process.

[FischOderAal]

Maybe L2 latency is higher due to unmature process

this reminds me of the Tbred A days.... now lest wait for the B

me thinks the same.

2800mhz with stock cooler isn't that bad, or am I wrong? though it doesn't look like the OC monster everyone was hoping for

and I'm confused about the high voltage, too. doesn't make much sense to me. ok, AMD can now put more DIEs on one Wafer, but this wasn't the only advantage we were expecting, right?

[turbox997]

Well, it seems that which was hypothesized and predicted has indeed come true.

Many on the forum expected the 65nm cpu's from AMD would not clock well initially as it repeated itself from 90nm transition...keyword "initially".

Hopefully when things mature we can see some real good stuff pressing out. It does make me question though....how soon can we see a serious threat come for Intel?? My expectations for K8L aren't very high.

[nn_step]

Does this means that AMD have had and still have problems with the 65nm SOI-3 and that the 65nm SOI-3 is slower than the 90nm SOI-2?


No, it isn't a typo. The latency is measured in cycles, which is same dimension as Hz's.

cycles and Cycles/second aren't the same thing

[gOJDO]

yeap, you are right.
Hz should be replaced with cycles.

[agenda2005]

The higher latency might be due to longer pipeline. AMD might have lengthened the pipeline to start the MHz race all over again.

The clocks that Conroe and Allendale are hitting seems to be putting AMD in a panic mode. There is just not much you can do to fill up a 12-stage pipeline in K8 anymore. The design have reach saturation and all you get is a diminishing return.

Higher clock just give out more heat without any increase in performance to justify it. I'm guessing a 16-20 stage pipeline for those new brisbane core. http://www.digitimes.com/bits_chips/....dailytech.com
SEE THE LAST QUESTION/ANSWER.

Anandtech might have been provided a lowly clocked and highly volt chip to conceal AMD's secret here.

[kemo]

Something weird in that review E6600 consume less power that E6300

[cky2k6]

amd is not starting any mhz race over, the higher latency is so that they could get higher yields. think about it, this process is mostly done to increase shipments to oems, who dont give a rats ass about a 5% difference in a few apps. k8 isnt anywhere near the performance crown, so its not really that damaging, for those who still like amd, theres revision f3 chips to play around with. amd will make a reall effort when star comes, before then theyll take higher yileds over a few cylces higher latency.

[nn_step]

The higher latency might be due to longer pipeline. AMD might have lengthened the pipeline to start the MHz race all over again.

The clocks that Conroe and Allendale are hitting seems to be putting AMD in a panic mode. There is just not much you can do to fill up a 12-stage pipeline in K8 anymore. The design have reach saturation and all you get is a diminishing return.

Higher clock just give out more heat without any increase in performance to justify it. I'm guessing a 16-20 stage pipeline for those new brisbane core. http://www.digitimes.com/bits_chips/....dailytech.com
SEE THE LAST QUESTION/ANSWER.

Anandtech might have been provided a lowly clocked and highly volt chip to conceal AMD's secret here.

umm that was not even close to being accurate.
AMD has a (in theory) max IPC of 4.5 (1.5 FP, 3 Int)
Conroe has a (in theory) Max IPC of 7 (2 FP, 5 Int(under ideal circumstances))
Now the average IPC at any given time is less than 1.7
In standard programming IPC rarely exceeds 2.5
So in pure logic means that the IPC isn't even being used up yet.
The only logical improvement that remains is to be more efficient in prefetch and to issue more to be processed

amd is not starting any mhz race over, the higher latency is so that they could get higher yields. think about it, this process is mostly done to increase shipments to oems, who dont give a rats ass about a 5% difference in a few apps. k8 isnt anywhere near the performance crown, so its not really that damaging, for those who still like amd, theres revision f3 chips to play around with. amd will make a reall effort when star comes, before then theyll take higher yileds over a few cylces higher latency.

Thank you, that is spot on, remember the slowest part (cache/processor) determine the top speed of the processor

[gOJDO]

The higher latency might be due to longer pipeline. AMD might have lengthened the pipeline to start the MHz race all over again.

The pipeline on all K8 CPUs(all revisions, all prodcution processes) has same length: 12/15 ALU/FPU stages.

Higher clock just give out more heat without any increase in performance to justify it.

CPU perfromance = IPC(instructions processed per clock) x freqfency. Performance can be increased by increasing IPC, by increasing freqfency or by increasing both.

AMD has a (in theory) max IPC of 4.5 (1.5 FP, 3 Int)
Conroe has a (in theory) Max IPC of 7 (2 FP, 5 Int(under ideal circumstances))

Nope.
K8 has in theopry max IPC of 3, while Core2 has 5(in case when macro-op fussion is used). K8 is a 3 issue core, Core2 is 4+1 issue. It is impossible to have more instructions retired than the decoder can decode.

[Flak Monkey]

Something weird in that review E6600 consume less power that E6300

They prefaced that earlier in the review.

The impact of higher voltages on power consumption also applies to Intel as well. As you will see in our power comparison, in a number of cases our Core 2 Duo E6300 required even more power than the E6600 we tested last time. The reason being that our E6300 sample runs at a core voltage of 1.325V vs. 1.2625V for our E6600 sample. Just things to keep in mind as you look at the power results over the next few pages.

[Piotrsama]

Any thoughts on die size? (2nd page of the article)

What makes Anand think this is possible?

this is AMD's first 65nm chip, and AMD tends to make many improvements to its manufacturing process over time. The chip we're comparing Brisbane to was made at the pinnacle of AMD's 90nm manufacturing cycle, so it's quite possible that, with time, AMD will improve its 65nm process to the point where a smaller Brisbane would be possible. Until we can get a more technical explanation from AMD, that's the best we can report on this issue

Maturing a process means that you get a better ocer chip, or better power consumption..... but I never heard of reducing die size (with same amount of transistors, and same nm. process).
Strange....

[Theli]

cycles and Cycles/second aren't the same thing

Yes they are, just like meters and meters per second are the same thing. Yesterday, the wind blew 4 meters.

Anyway, does anyone know how the price is to compare between the 90nm versions and the 65nm versions?

[zir_blazer]

Hz refers to cycles per second, not absoloute clock cycles. The quoted values would equate to cache latencies of 83ms and 50ms, which is a bad typo

Tom

Fixed it, didn't know this.


About the increased Cache L2 Latency, I got a theory. If I recall correctly, the Prescott 2M was capable of reaching on average higher Frequencies via overclocking than the Prescott could. Without improved quality yields, and supposingly than the Cache L2 was the slower component from the Prescott Core and didn't allowed it to reach higher Frequencies, slowing the Cache L2 Latency would possibily work like if you was raising the Timmings on a Memory Modules, you trade Timmings for higher Frequencies. If in the K8 the Cache L2 was also the slower component, raising the Latency would allow it to reach higher Frequencies. However... 65nm K8s doesn't overclock further than what current 90nm Cores does, yet the Cache L2 Latency is higher. Maybe they had to increase the Cache L2 Latency just to being able to reach current Frequencies. A very bad sign if what I'm saying is right, indeed.

[nn_step]

Maturing a process means that you get a better ocer chip, or better power consumption..... but I never heard of reducing die size (with same amount of transistors, and same nm. process).
Strange....

You also forget the empty space on some dies. Routing issues in design. Changes in the mask. there are literally thousands of ways to reduce Die size even with the same process.

[metro.cl]

i can only say one thing

[ozzimark]

The pipeline on all K8 CPUs(all revisions, all prodcution processes) has same length: 12/15 ALU/FPU stages.

i was under the impression that the FPU was 17, not 15

[nn_step]

i was under the impression that the FPU was 17, not 15

you are correct
Int =12
FP = 17

i can only say one thing

what is so important about Bad memory timing?
Besides the fact that it would seriously effect performance

[metro.cl]

you are correct
Int =12
FP = 17

what is so important about Bad memory timing?
Besides the fact that it would seriously effect performance

bad freq not timings, it just sucks if you ask me

[nn_step]

bad freq not timings, it just sucks if you ask me

compared to what it could be doing you are correct.
a 6 Divider isn't too much of a stretch.
but what is bugging me is the fact they are running 5-5-5-18-T2
Which is nearly doubt what it could be. Since Latency matters more than Bandwidth for AMD (for the most part)

[zakelwe]

amd is not starting any mhz race over, the higher latency is so that they could get higher yields. think about it, this process is mostly done to increase shipments to oems, who dont give a rats ass about a 5% difference in a few apps. k8 isnt anywhere near the performance crown, so its not really that damaging, for those who still like amd, theres revision f3 chips to play around with. amd will make a reall effort when star comes, before then theyll take higher yileds over a few cylces higher latency.

AMD are saying it is for possible larger than 1MB cache later on rather than yeilds. I wonder why they would want very large cache, currently their architecture allows efficient use of small amount of cache, say 512.

Regards

Andy

[Fred_Pohl]

Performance and efficiency are still both Intel's fortes thanks to its Core 2 lineup, and honestly the only reason to consider Brisbane is if you currently have a Socket-AM2 motherboard.

Sums it up quite nicely.