3/4/3/9 VS 4/4/3/9 - no improvement???

[mike]

I ran a couple of test today with 2X1GB of D9s and was VERY surprised to see that 3/4/3 was slower/equal to 4/4/3 running 8m/32m SuperPi.

Never put too much thinking into 3/4/3 timings before - but since Corsair are being run often on these timings - it seems to be more smoke and mirror than anything useful at first glance to me.

I have screenies but can't upload them ATM.

Anyone has done some compares with 6400C3 by any chance? If not I will look more into this later.

[ZX7891]

What motherboard was this done on?

[N00B]

the improvemente is around 5% so i think its better cas4 , cause you can get higher clock's.

[Gautam]

That's odd...somehow I always have trouble keeping up with even 2x512 CAS 3 results at 4-2-2-x...I think. Maybe some 3D tests are in order as well?

If anything some screenies are in order.

[ozzimark]

with D9GMH, i've actually found that what the sticks can do at 3-4-3, it's usually within 3-5mhz of the max speed at 3-3-3... might just be me though

[mike]

here's the pics:

3/4/3/9 8m:



4/4/3/9 8m:

[mike]

32M:

3/4/3/9



4/4/3/9

[ZX7891]

i think the gigabyte DS3 doesnt do something with CAS latencies correctly, because no matter what CAS i set in bios, it shows cas 3 in windows

[mike]

1m 4/4/3/9

[mike]

i think the gigabyte DS3 doesnt do something with CAS latencies correctly, because no matter what CAS i set in bios, it shows cas 3 in windows

depends on the divider you use - 1:1 is totally screwd up - but if you use memset you can change it.

4:5 - 3:4 are much better dividers if your mem can handle it.

But again - it might have to do something with the board - not sure. I appear to be in the 1066 bootstrap ( memset displays it - and I know hte memory can take it even further on the old P5WD2-E.

It might be worth looking into COrsair's 6400C3 whether it is all smoke and mirror or if they handle 3/4/X/X better?

And GAUTAM - get off my butt with times - I was just doing stabilty testing - not bench runs

[Tulatin]

Words of the wise - when benching, disable/close Easytune. It added about 1s to my S-Pi 1M

[sierra_bound]

Asus P5W DH & Corsair 6400C3. 430 1:1. After running 3-4-3, I went back into BIOS and changed Cas Latency to 4, then ran 8M again. The secondary timings you see are what came up after booting into Windows. No tweaking done.

I've found the difference between CL3 and CL4 is very small with DDR2. RAS# to CAS# is generally much more important.

3-4-3



4-4-3

[mike]

Words of the wise - when benching, disable/close Easytune. It added about 1s to my S-Pi 1M

Thanks for the tip - but wasn't benching

And GAUTAM - get off my butt with times - I was just doing stabilty testing - not bench runs

[mike]

Asus P5W DH & Corsair 6400C3. 430 1:1. After running 3-4-3, I went back into BIOS and changed Cas Latency to 4, then ran 8M again. The secondary timings you see are what came up after booting into Windows. No tweaking done.

I've found the difference between CL3 and CL4 is very small with DDR2. RAS# to CAS# is generally much more important.
[/img]

thanks a bunch for doing this Sierra_bound - I can't run atm and was hoping for someone to show similar result!

It appears almost that RAS# to CAS# overrules CL once RAS# to CAS# is greater than CL. From your 8m times it also becomes pretty appearant that CL has no impact whatsoever i such case scenario


The board BTW was Gigabyte 965-DQ6

[Vapor]

I'm honestly not noticing much of a difference between 4-4-4-10 and 4-5-5-14

Seems random for which one is faster....

[Kunaak]

P4's have never really been too effected by CAS.
this has been true since my first day with my first intel CPU the 2.8C.

bandwidth, is almost always more important then cas alone in the cas of Intel stuff.

[Gautam]

I agree with the premise completely, and don't worry no heat about the times. (I don't take anything done with Netburst seriously anyways )

But my eyebrows are raised. 520MHz+ CAS 3 with that ram?? IIRC the highest CAS 3 ever done on anything but the Bad Axe was in the 470's. The speeds just look so high, I'm not sure I trust that the board is reporting the correct CAS value. If it is though, we need to talk.

btw, Eric, I hope you were running longer calcs than 1M. Conroe is "too much" for 1M and is barely affected by anything on the RAM side whatsoever.

[VictorWang]

I've tried comparing 3-3-3-1 vs 4-4-3-1 vs 4-3-2-1 pi_32m
fsb=300mhz
ram:
450mhz 3-3-3-1=500mhz 4-4-3-1<500mhz 4-3-2-1 in pi_32m

4-3-2-1 about 10sec faster than 4-4-3-1 , fat d9 always wins if you give them more volt

[mike]

But my eyebrows are raised. 520MHz+ CAS 3 with that ram?? IIRC the highest CAS 3 ever done on anything but the Bad Axe was in the 470's. The speeds just look so high, I'm not sure I trust that the board is reporting the correct CAS value. If it is though, we need to talk.
.

I actually just tried to run some Corsair 6400C3 instead of the ram I ran before and wasn't able to get above 460 with 3/4/3/9 - so I have to assume that the CL3 is reading correctly.

I've tried comparing 3-3-3-1 vs 4-4-3-1 vs 4-3-2-1 pi_32m
fsb=300mhz
ram:
450mhz 3-3-3-1=500mhz 4-4-3-1<500mhz 4-3-2-1 in pi_32m

4-3-2-1 about 10sec faster than 4-4-3-1 , fat d9 always wins if you give them more volt

WOW - only 10 secs faster in 32M - I would have assumed it would be more pronounced than that. Time for me as well to look deeper into this subject

[_damien_]

I've found the difference between CL3 and CL4 is very small with DDR2. RAS# to CAS# is generally much more important.

As a general rule, CAS latency is the most important memory parameter, but exceptions are found in certain unideal cases.

For example, under the following scenarios, 3-4-3 would yield worse throughput than 4-3-3:

Command rate: 2T

Bank interleaving: enabled

Additive latency: 0 / disabled

Burst length: 8


The above settings combined with CAS 3 - tRCD 4 will cause a bubble of 4 I/O time slots between the output bursts from different banks, while CAS 4 - tRCD 3 would result in only 2. In the first example, the read-commands would collide with the activate-commands, thus delaying the assertion of future bank/row activations.


However, when AL is correctly set, the output sequences will usually be uninterrupted even though the command rate is forced to 2T. Quite often, tighter timings hightens the risk of command collisions, because there would be fewer cycles between each new command. But on the other hand it should be noted that certain combinations yield optimal throughput even when AL is disabled. The combination of the tight 3-2-2-x-2T is a great example of that.

Factors like command rate, idle cycle limit, access pattern, active-to-active-timings and burst length may affect its importance, but CAS latency is basically the most important setting, simply because it is involved in every read operation.

[sierra_bound]

Theoretically what you are saying is correct. But there's a difference between theory and reality. If I have a chance, I will run 8M again at 5-4-3 to make a point.

Of course 4-3-3 is going to better than 3-4-3. I think all benchers know that. People who bench usually do a lot of experimenting with timings.

With DDR2 the most important factor of all is memory speed. Using the 4:5 ratio will give a big boost with Conroe.

[Gautam]

_damien_, your posts are always a pleasure to read.

But...

Theoretically what you are saying is correct. But there's a difference between theory and reality.

I couldn't have said it better myself. CAS has on the whole been quite unimportant for us enthusiasts for nearly every platform.

Most of us are in fact running with all your "unideal" criteria. Though even I am rather surprised at the results. Gonna have to get down, install Windows and run some 3D in similar fashion.

And Mike...we definitely have to talk...mind your pm's plz.

[sierra_bound]

I decided to take a different tact. What's the difference between RAS# to CAS# Delay at 3 versus 4 using same memory speed?

3-4-3


3-3-3


As you can see, only a slight difference, about the same as the difference between CL3 and CL4. Therefore I guess I can argue that RAS# to CAS# is just as important (or non-important) a factor as Cas Latency.

Still, 3-3-3 would probably be around 7 secs. faster in 32M. Could be the difference between 13mins 59 secs and 14mins 6 secs.

[_damien_]

Theoretically what you are saying is correct. But there's a difference between theory and reality.

I manage not to see it that way. If no theoretical explanation can be found, that's probably because we don't know all the details.

Of course 4-3-3 is going to better than 3-4-3. I think all benchers know that. People who bench usually do a lot of experimenting with timings.

Now you seem to be completely forgetting my scenarios, even though you said I was right. Isn't it true that most benchers don't reveal which settings they use for BL and AL at least? Believe me, those two settings are crucial to my examples. So you'd have to know exactly which settings were behind all those benchmark results before making that conclusion.

With DDR2 the most important factor of all is memory speed.

We've been over that one. That's not a characteristic of the memory architecture. But of course, there is a connection between clock frequency, latency values and time.

[sierra_bound]

In an earlier post, you said "CAS latency is the most important memory parameter, but exceptions are found in certain unideal cases."

I'm not sure what you consider to be unideal cases. I've just shown that changing Cas Latency from 3 to 4 yields about same time difference as changing RAS# to CAS# Delay from 3 to 4. This would tend to refute your claim that Cas Latency is the most important parameter. Or am I missing something here?