Core Multiplexing technology???

[JumpingJack]

I dont think anyone ever doubted (not that ive seen anyway) that code could be paralelized by hardware. What was doubted (and rightly so) is that one instruction could be split to execute on 2 cores.

David Kanter of RWT didn't believe so:

http://www.realworldtech.com/forums/...9280&roomid=11

Some bought it out of the shoot, others (like myself) were simply not convinced choosing to be more skeptical. It took me a few hours over two weekends to dig up enough literature and educate myself on the principle.

Actually, some of the enthusiast HW sites are exclaiming that AMD with RHT will meld 2 cores to mimic 1 virtual core, the Inq. claims it will take two 3 IPC (issue) cores and make one 6 IPC (issue ) core. This is not quite true, in fact the peformance speed up is governed by Amdahl's Law for the most part and how effectively the thread can segment and execute correctly. A 2x gain is quite not possible in a normal single threaded application. David Kanter does a good job above rationalizing the two different architectural states of each core.

[p360stick]

if this is true the cpu will be fast as hell

[Haltech]

So would this actually require a driver to be installed into the actual OS as well as a BIOS option?

[nn_step]

So would this actually require a driver to be installed into the actual OS as well as a BIOS option?

Preferably just a Bios update. kind of how early dual core AMD samples needed a bios update for the computer to detect the second core...

[MAS]

802.11g
802.11g is a proposed standard, describing a wireless networking method for a WLAN that operates in the 2.4 GHz radio band (ISM--Industrial Scientific Medical frequency band). By using OFDM (Orthogonal Frequency Division Multiplexing) technology, 802.11g-based WLANs will be able to achieve a maximum speed of 54 Mbps. 802.11g-compliant equipment, such as wireless Access Points, will be able to provide simultaneous WLAN connectivity for both 802.11g and 802.11b equipment.

further -

OFDM is nothing new — its core multiplexing principles have been applied to everything from satellite broadcast to ADSL. Over the last decade, the technology has played a critical role in wireless, forming the basis of the IEEE 802.11a standard and, most recently, the critical multiplexing scheme for the WiMAX Forum's next generation of wireless broadband specifications.

http://forums.overclockers.ru/viewto...dcecf98e79ad8c

if bad axe has 802.11 integrated, bios item core multiplexing can just control 802.11 -)))))))))))

[MAS]

though phrase "core multiplexing principles" can be explained also as "fundamental multiplexing principles" - if so, I am sorry

[TarTheDark]

This thread made it to TweakTown

http://www.tweaktown.com/index.html#news_5891

[vapb400]

lol it looks like core multiplexing was removed from the most most recent bios.

[Burdman]

I don't have a Badaxe so I don't know, but didn't it just say they moved it from the main page... so the option could be on a different one? (I have no clue, just stabbing around in the dark so to say).

[MAS]

do you still beleive in intel virtual core?
unknown bios menu item is not a proof of its existance
one more myth

[gone_fishin]

I don't have a Badaxe so I don't know, but didn't it just say they moved it from the main page... so the option could be on a different one? (I have no clue, just stabbing around in the dark so to say).

They hid the BIOS option. It is still there but hidden. Open the Bios with ITK to see.

[MAS]

somebody, send me this bios image
i will disassemble it and look at it's internals
just interesting

[Scyphe]

Wow, rumourmill is churning out a lot of pointless stuff from the gutter.. Homemade pictures and people believe in it.. Yes, "added for effect" sure made the wanted effect.

This is what Intel spokesman said when asked about it:

“We will support the disabling of one core in BIOS in a future BIOS rev.,” said Daniel Snyder, a spokesman for Intel Corp., when asked about the background of the technology. This means that once one core is disabled, the whole 2MB or 4MB cache reservoir on microprocessors that have shared level-two (L2) cache will be usable by one processing engine, which should boost performance in applications that cannot take advantage of two executing cores.

It is highly-likely that the feature will only work on the upcoming Core 2 processors code-named Conroe, which have shared L2 cache between its cores. It is also likely that the capability will allow quad-core chips to act like two dual-core processors in situations when four processing engines cannot be used efficiently.

[Cooper]

Wow, rumourmill is churning out a lot of pointless stuff from the gutter.. Homemade pictures and people believe in it.. Yes, "added for effect" sure made the wanted effect.

This is totaly different BIOS option (more related to power saving) and been known for a while now

[Scyphe]

Yes.. and it's probably what all this misdirected hullaballo is all about. But what do I know (or anyone else for that matter).

[Mr. Tinker]

yes we do

EDIT: pictures added for effect.

Conroe: 2 -> 1 core possible



Kentsfield: 4 -> 2 cores possible



-FCG

Congratulations, these diagrams are on all the enthusiast sites.

[MAS]

these diagrams are on all the enthusiast sites

but it doesn't work and scarcely will work

[i||uSi0n^]

did you guys even read what Intel said? They said core multiplex disables one core so app can take full advantage of the shared cache...

where did u read that ? link please ?

i||uSi0n^

[Thorburn]

did you guys even read what Intel said? They said core multiplex disables one core so app can take full advantage of the shared cache...

Thats not Core Multiplexing, thats the SW Single Core option in the BIOS.

[PetNorth]

No, as far as I know with SW Single Core "enabled" in BIOS, one core is always disabled.

CMT lets to use the whole cache to one core when single thread app is running, but both cores are "active".

They are different things.

[[XC]Atomicpineapple]

Quote me

SW single CPU does indeed cause the PC to boot and use only 1 core. SW single core gave a slightly faster Pi time tho that may be an anomaly.

Quote Cooper in next post down

Don`t think it`s a anomaly. L2 is shared, so you have all 2MB just for one core -> better result.

Given that explaination it looks like SW core disable does shove all the cache over to 1 core, and multiplexing is somethign else, probably as FCG described

[PetNorth]

I don't think it's the same explanation. With SW single core enabled in BIOS, one core is *ever disabled*, so you have only one core, and yes, because shared cache, the only core enabled uses all cache.

With CMT both cores are *ever enabled* but when a single thread app is running, CMT lets that the core where it runs uses the whole cache too.

I extract this possible explanation of what CMT is, from here http://www.xbitlabs.com/news/cpu/dis...627095448.html

[yoti]

Maybe here we have answer?
http://www.anandtech.com/tradeshows/...spx?i=2507&p=7

[theteamaqua]

so how is single core different from this core multiplex technology?? they are different right?? CMT turn multi thread into 1 core or 2 core (kentsfield) right??

[Thorburn]

so how is single core different from this core multiplex technology?? they are different right?? CMT turn multi thread into 1 core or 2 core (kentsfield) right??

If its the same as what is shown in the Anandtech article then Core Multiplexing would allow an idle core to do speculative threading work instead of sitting doing nothing. If you have multi-threaded code then it goes to work on the other thread instead automatically.
Single core mode turns off the second core completely, no operations carried out whether you have multi-threaded code or not.