Quote:
Originally Posted by rosco
Thermal gradient within the die can achieve 20~40+ °C between the hottest and the coldest point, depending of the load.
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I believe that is the story of the fish that grew from 10inches to 40 inches, unless you can produce a document showing otherwise. I had read the paper when it first came out, but took a while to find it again. The paper published by senior intel engineers and architects of the core duo processor titled "Temperature measurement in the IntelŪ CoreTM Duo Processor" shows the die map, and a chart revealing the temp gradient of roughly 150 different load programs they tested.
Quote from paper.
"In order to evaluate the DTS temperature reading, we performed a study to identify the impact of different workloads on the difference between diode and the hot spot, as measured by the DTS. A set of workloads including all SPEC-2K components and other popular benchmarks and applications, at single thread and multithread were executed on the CPU. Several iterations were done to reach a thermal steady state and then the diode and DTS temperatures were measured. Before taking the measurement, a calibration process has been performed, leaving only the temperature offset. Figure 5 shows the offset between the analog diode and the hot spot, as measured by the DTS... It also can be noted that some workloads display high temperature gradients (largest ~5.2C)
while others have no offset."
Highlights:
Gradient from Die hot spot to central diode is 0C at idle and was measured 0C at roughly 15% of the "popular" load programs/benchmarks tested after steady state load was reached. Nearly a third of load benchmark/programs had a gradient less than 1C, and the maximum gradient between hot core and cooler central diode was ~5.2C, likely on programs like TAT, described with such a gradient in another article. The hottest transient gradient measured from hot spot on one core to an inactive core was 10C, using TAT like program or hotter, and this was on a larger cpu than 45nm.
What intel describes as a large hot spot is again stated in their article describing the reasoning between putting DTS on die versus junction..."The better accuracy translates either into 3%-7% higher performance or into improved ergonomics" or "In desk-top computers the impact is even higher due to the lower thermal resistance and 1C accuracy translates into 2 Watt of CPU power." Intel considers this 5C max gradient seen between hot spots and junction to be worth the move to die sensors.
The only possibility imo that tjmax was still 105, was the potential hot spots. But at idle, and even at load on a large number of the tested "popular benchmarks/programs the gradient was measured 0C from core to between cores, even at high temps 93% of tjmax.
The only other gradient, from sitting on core to Tcase was measured at 0.4C in previous link.
45nm seems to have less gradient, illustrated by Unclewebb showing no more than 1C difference between loaded core an idle core.
I think the burden of proof is clearly on those who want to claim a gradient larger than 1C exists from core to tcase at either idle or steady state load for moderate load programs.
http://eda-publishing.imag.fr/spip/IMG/pdf/TMI23.pdf
good read