I post tgdaily's article first and this post gets stickied? WTF?Originally Posted by GoThr3k
I post tgdaily's article first and this post gets stickied? WTF?
I think I posted AMD's reply to Fabtech's original article in the thread that got deleted:
Advanced Micro Devices is not delaying 45-nanometer manufacturing, according to the company, which is trying to correct an erroneous report on a blog.
"We are still on track to produce the first (45-nanometer) products by mid-2008," said Gary Silcott, an AMD spokesman. The company will have "pretty good volumes" of 45-nanometer chips by the end of 2008, he added.
The also claim that the problems with Barcelona have been with finalizing the chip design, not with their manufacturing process:
Analyst
Dirk, I had a question for you. On the Barcelona ramp you said it materialized a little slower than anticipated and your speed grades haven't been targeting the top end right off the bat. There has been some speculation that perhaps your yields on 65 nanometer specifically as it relates to Barcelona is the issue here.
Any comments you would want to make or a different explanation you would want to offer up on why Barcelona's speed grades aren't as fast as you would like them to be?
Dirk Meyer
First of all, I'll say that the basic silicon yields of Barcelona are right where we expected them to be. They're right line on line with the previous 65 nanometer products from a deep activity and overall yield perspective.
The issue has been simply one of tuning the design to the technology so as to support a high volume ramp. It is that particular issue that caused us to take a few extra weeks before we turn on the high volume ramp in the middle of this quarter.
Analyst
In other words, there's nothing endemic to your process technology that is problematic or which might spill over to your 45 nanometer ramp?
Dirk Meyer
No. The minor issues we've been experiencing have nothing to do with the process technology or the manufacturing capabilities. It is all a matter of wedding the design to the technology so as to be able to ship in volume.
Analyst
Anything else you could share along those lines in terms of details as what the issues have been in wedding your designs with your process technology?
Dirk Meyer
I don't think in this forum.
badass, i hope AMD can put out some good clocking 45nm chipsthat would make my day seeing them put it back on Intel cus competition is key and prevents stagnation within the industry which in the end always benefits us
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If AMD can make a production quality < 2.6GHz quad core this year why would they prefer to sell it as a desktop CPU instead of a high margin server CPU?
I am assuming the barcelona and phenom cores are the same? If my assumption is true then why the big difference in clock speed between barcelona and phenom?
They are making < 2.6GHz chips right now. 2GHz < 2.6GHz
If you mean > 2.6GHz (greater than), well AMD usually doesn't release the fastest part first, also leaves more "breathing room" so to speak in their server chips and binned them lower even if they were capable of higher speed (which is partly why the older s939 opterons for example would usually OC very well). Why they do I'm not sure.
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actually the reason AMD NOR Intel releases their top bins at first is because the yields are not perfect and take months before improvements are availableThey are making < 2.6GHz chips right now. 2GHz < 2.6GHz
If you mean > 2.6GHz (greater than), well AMD usually doesn't release the fastest part first, also leaves more "breathing room" so to speak in their server chips and binned them lower even if they were capable of higher speed (which is partly why the older s939 opterons for example would usually OC very well). Why they do I'm not sure.
Fast computers breed slow, lazy programmers
The price of reliability is the pursuit of the utmost simplicity. It is a price which the very rich find most hard to pay.
http://www.lighterra.com/papers/modernmicroprocessors/
Modern Ram, makes an old overclocker miss BH-5 and the fun it was
nobody cares to explain why SOI is so difficult on 45nm?
Too technical for me to know or answernobody cares to explain why SOI is so difficult on 45nm?
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The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10 - 15% increase to total manufacturing costs but outside of that, there is little reason for difficulties outside of specific implementation details (Z-Ram for Example)nobody cares to explain why SOI is so difficult on 45nm?
Fast computers breed slow, lazy programmers
The price of reliability is the pursuit of the utmost simplicity. It is a price which the very rich find most hard to pay.
http://www.lighterra.com/papers/modernmicroprocessors/
Modern Ram, makes an old overclocker miss BH-5 and the fun it was
savantu explained it/posted a link, but it got deleted...nobody cares to explain why SOI is so difficult on 45nm?
Last edited by Hornet331; 10-25-2007 at 09:49 AM.
so the use of SOI shouldnt be the reason for the high leakage on the 65nm parts?
How can your article dated 18th of October, be AMDs answer to the fabtech article i posted dated 22nd of October?
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please,don't act like a child,amd said clock per clock,and in some workloads.....
if your only intention is to flame and to cause a amd vs intel war,please go spam another thread
its about 45nm here....
Show us that official claim from AMD?
Why am i not surprised
Btw check AMD section, K10 seems to overclock afteral and seems to scale not linear afterall...
First link : http://www.news.com/AMD-Go-to-Barcel...3-6152645.html
"We expect across a wide variety of workloads for Barcelona to outperform Clovertown by 40 percent," Allen said.
To blame AMD because this sentence has been transformed to "We expect across [a wide variety of workloads for] Barcelona to outperform Clovertown by 40 percent," Allen said, it's a little lame.
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..savantu explained it/posted a link, but it got deleted...
Back on topic :
http://www.semiconductor.net/article/CA6464480.html
As late as mid 2007 AMD was still debating what to do at the 45nm node and some think they will greatly reduce the process gap with Intel in 2008. LMAOBulk or SOI? AMD Considering Its Options
David Lammers, News Editor -- Semiconductor International, 7/31/2007 12:30:00 PM
Advanced Micro Devices (AMD, Sunnyvale, Calif.) is still mulling whether to use silicon on insulator (SOI) or bulk silicon technology for its future high-end and mobile products.
“This is in the exploratory phase, and AMD has not made any statements about when it would make a decision to produce next-generation processors in bulk or SOI,” a spokesman said, adding that AMD technologists are asking questions that “are not answered yet, so we are leaving the question open as they look at the issues.”
During a July 26 meeting, AMD executives described the company’s technology and product roadmaps. Doug Grose, senior vice president of manufacturing and supply chain management, said that AMD is “evaluating the mix” of SOI and bulk technologies for 2009 and beyond.....
And for SOI challenges :
http://www.semiconductor.net/index.a...A6464480#69173
One of the major differences between the SOI and Bulk technology for the 45nm and beyond is to control the electostics or the short channel effects. For the bulk technology used by Intel the quantum confinement of carriers is controled by a combination of Hallow source/drain implant, and retrograded channel/substrate doping.
On the other hand, for the SOI technology the quantum confinement of carries in inversion layer is carried out by physically reducing the SOI thickness, Tsoi by narrowing the space between the gate oxide and the buried oxide. To mitigate the short channel effects, 45nm SOI may require 50nm~40nm Tsoi, 30nm~20nm Tsoi for 32nm, and 10nm or less Tsoi for 22nm technology. Such a thin Tsoi causes significant carrier mobility degradation and increase in threshold voltage, Vt. Furthermore, for the scaled devices, the strain induced mobility enhancement techniques become less effective.
This is particularly more so for the thin SOI technology simply because in such a thin ~10nm junction and isolation depths, and channel inversion layer thickness it is extremely difficult to implement GeSi S/D junctions and a large lattice mismatch induced by the relaxed Ge-Si substrate in the channel.
Even for the 45nm SOI technology, the manufacturability of the strain induced mobility enhancement techniques used for 90nm and 65nm may not be feasible. In this respect, the SOI technology for the 45nm and beyond has a significant disadvantage over the bulk technology. IBM and AMD are at the crossroad today to determine extenderability as well as manufacturability of the SOI technology for 45nm and beyond.
The conversion from the SOI to the bulk 45nm technology node has enormous technological and manufacturability challenges. This is because IBM and AMD do not have the required learning experiences such as process, design, reliability and device yield gained from the 90nm and 65nm bulk technology development and mannufacturing. Furthermore, two major new materials were introduced in the bulk 45nm technology: the thermal oxide, SiO2 that was used for 40 years is replaced by HfO2, and the polysilicon gate that was used for over 30 years is replaced by the metal gate.
Today Intel is the only company that is manufacturing the bulk 45nm. If that is true, Intel has enormous advantages over its competitors, particularly if IBM and AMD have to adopt the 45nm bulk technology. This is because Intel must have resolved most of the device, process, reliability, and manufacturability issues as a result of introduction of the new materials and processes.
When the new materials and processes like HfO2, metal gate, and their new processes are introduced, new or unknown faiure mechanisms will be also introduced. Therefore, it is crucial to design test structures so as to bring out the unknown failure mechanisms for early detection, and develop effective E-test and reliability test screens. Such experiences gained through the 90nm and 65nm bulk technology development cycles will give an edge to Intel in successful development of the 45nm technology and beyond.
Last edited by savantu; 11-17-2007 at 12:06 PM.
@ Savantu, could you summarize what the article means for AMD? They do have a year (all of 2008) to make that decision and face those challenges, based on which decision they make.
@ Zornundo, check first post
@ Periander, well, the biggest disconnect with respect to AMD's Phenom X4 today is that the general public don't have access to results that a limited number of people do.
@ Cooper, ty
All I can say is, yes, you'll see it perform quite well with some new "enhancements" with respect to ocing them.
Perkam
Let's hope so. Same process, same size as Brisbane and we've seen some Brisbanes hitting 3.5ghz on air; no reason to believe that the quads can't reach upwards of 3.0 ghz as well! It'd be nice to have an AMD quad setup under my Christmas tree this year.
As quoted by LowRun......"So, we are one week past AMD's worst case scenario for BD's availability but they don't feel like communicating about the delay, I suppose AMD must be removed from the reliable sources list for AMD's products launch dates"
Yeah, I can see where that's confusing. It was the reply to Fabtech's "original" article. Fabtech originally speculated that there would be no 45nm from AMD until 2009, and AMD corrected them. Fabtech somehow didn't see AMD's response before their second article (the one you posted), so they only talked about the conference call. They missed the fact that AMD expects to have "pretty good volumes" of 45nm by 2H 2008.
I guess it depends on what you mean by "produce." It sounds like there won't be any chips available for sale until mid-2008 (which could very well mean September). But they are making 45nm chips now, and expect to ramp production in 1H 2008:
Dirk Meyer
We're looking forward to ramping 45 nanometer product production in the first half of next year
...
First, we are on track relative to having basic yields in place in our factories on material that we're running today. We're building 45 nanometer microprocessors as we speak and those two facts give us increasing confidence in the public statements we've been making for some time around our intent to be starting our production ramp of 45 nanometer processors in the first half of next year.
I think it's less that they "missed" what AMD said and a lot more they simply don't find AMD's statements credible. Throughout AMD's 2006 conference calls they repeatedly stated that they would be shipping 65nm K8s before the end of the year. Although Brisbane was launched in December, it was pure paper until late January.
Things aren't so simple.
You have 2 main types of leakage in a transistor : gate leakage and subthreshold.
Subthreshold was the bigger one in 130 ,90nm but at 65nm gate leakage took over.SOI helps with subthreshold leakage and a few other things, but has no effect on gate leakage and brings a different set of problems.
The problem : once you get to 65nm and lower gate leakage increases dramatically.As a result , SOI's usefulness in reducing leakage is getting smaller and smaller.Also you can fight subthreshold leakage with circuit design techniques ( does Intel's Restrictive Design Rules ring a bell ? )
How do you fight gate leakage ? With metal gate and high-k dielectrics.These 2 things become a must have for a successful 45nm process.AMD lacks both at the 45nm node AFAIK .Intel virtually pushed back the problem by decreasing gate leakage by a factor of 10.
Now go back to my previous post and reread the comment on SOI problems with carrier mobility degradation and threshold voltage.
Basically it boils down to : AMD is FUBARed if they don't do something fast.Basically they are waiting for IBM to pull their a** out , yet IBM suffers from the same problems.
To give you a hint on AMD's problems , let's look at their 65nm process. Besides the official PR BS with "most advanced , high yields" the process is significantly different from what was expected.
In 2005 when AMD presented their tech papers on their 65nm process they reported a 1.2 nm thick oxide (the same thickness as Intel's 65 nm), yet Semiconductor.com reported (I saw at EETimes) just recently reversed engineered a barcelona chip in which AMD's oxide thickness was actually 25% thicker than Intels.
http://www.eetimes.com/news/design/s...leID=202100946...The transistor performances of Intel's Woodcrest and AMD's Barcelona appear to match fairly closely, with the Barce- lona's gate leakage about half that of the Woodcrest. This is not so surprising, as Intel uses a 25 percent thinner gate dielectric....
The 65nm node was the 1st process node where gate thickness stayed the same : this was done to keep gate leakage under control.
AMD even increased their oxide thickness from 1.2nm (90nm) to 1.5nm for 65nm in order to keep leakage under control.
Does this help with leakage ? Yes. Does it diminishes transistor performance ? Yes. Basically , their 65nm is excellent power wise , but clocks like sh*t.If you wonder why 65nm K8/K10 can't hit higher clocks , look no further.
But what do you do at 45nm ? Intel didn't bother with SiO2 , say hello to Hafnium which solved the problem , but AMD will have massive problems with oxide thickness/leakage/voltage as they try to hit clocks at 45 nm.
Last edited by savantu; 10-25-2007 at 09:38 AM.
All of this is pretty much speculation even by the experts. I'm not one of them and none of us probablya are, so I'll just wait and see.
I do know as far as clocking, I've seen a 5000+ hit 3.7G on air and a Barcelona get a 400mhz oveclock with stock votage on air. Maybe the experts were wrong about AMD's abitlity to get higher clocks.
The discussion is not about the current 65nm parts, its about the upcoming 45nm parts.
Also its nice that amd finaly has masterd its 65nm process, thought it should have been there from the start, not a year later.
Savantu,
You seem to know alot about soi vs bulk silicon. Do you work for a semiconductor company? You should visit scientias blog and discuss this material there.
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