Yeehaaa! E3110 TJ is 95 not 100 ! I`m happy:D
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Yeehaaa! E3110 TJ is 95 not 100 ! I`m happy:D
webb, rge, gurus, everyone,
I have a question - which may already be answered in this thread. Intel says Tcase (thermal spec) is 72.4C (C0) or 74.1C (E0) for E8400s. What does this mean as far as determining a maximum safe temperature for the cores?
I still cannot understand the relationship between intel's 72.4/74.1C limitations and the core temperatures measured by realtemp & coretemp.
IntelŪ Core™2 Duo Desktop Processor E8400
Processor Specifications:
sSpec Number:SLAPL
CPU Speed:3 GHz
PCG:06
Bus Speed:1333 MHz
Bus/Core Ratio:9
L2 Cache Size:6 MB
L2 Cache Speed:3 GHz
Package Type:LGA775
Manufacturing Technology:45 nm
Core Stepping:C0
CPUID String:10676h
Thermal Design Power:65W
Thermal Specification:72.4°C
VID Voltage Range:0.85V – 1.3625V
IntelŪ Core™2 Duo Desktop Processor E8400
Processor Specifications:
sSpec Number:SLB9J
CPU Speed:3 GHz
PCG:06
Bus Speed:1333 MHz
Bus/Core Ratio:9
L2 Cache Size:6 MB
L2 Cache Speed:3 GHz
Package Type:LGA775
Manufacturing Technology:45 nm
Core Stepping:E0
CPUID String:1067Ah
Thermal Design Power:65W
Thermal Specification:74.1°C
VID Voltage Range:0.85V – 1.3625V
Edit: Ahh I may have found my answer. Looks like intel assumes that when the top center of the E0 E8400's IHS reaches a temperature of 74.1°C, the temperature of the cores at that moment must be somewhere between 95C and 100C. I say this because of the mobile processors not having any IHS and Tcase being equal to Tjunction. When TM2 trips or activates prochot on the mobile core2duos, tcase max has been reached, and ironically it's the same as tjmax. So they have to be assuming that cpus with the IHS on them reach tjmax & tcase max simultaneously such as: 74.1C/100C. Correct?
Quote from intel:
"The thermal specification shown is the maximum case temperature at the maximum Thermal Design Power (TDP) value for that processor. It is measured at the geometric center on the topside of the processor integrated heat spreader. For processors without integrated heat spreaders such as mobile processors, the thermal specification is referred to as the junction temperature (Tj). The maximum junction temperature is defined by an activation of the processor IntelŪ Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached."
jaredpace,
I might have an answer to that a few hours from now after I finish drilling a small hole in the middle of intel heatsink, so I can check core, cpu temps versus tcase temps at idle and load. etching my cpu will not work, as I have to keep the surface probe perpendicular, so flat surface is against flat surface....so straight through the heatsink, fan and anything else that gets in way of my drill....btw...drilling through copper is a pain, may have to get sharper drill bit. It might be 1-2 degrees of error, but i have learned the IHS is such a good heat spreader that temps wont get more than about 1C difference across large area of it.
i bet you see something like this at maximum temps:
IHS thermocouple: ~73°C
Core temperatures: 95°C~100°C
Good news at least is that Nehalem should have an uniform DTS accuracy across temperature range.
looking forward to your results rge!
bingo!
after going through about 80 pics, different temps and notes best guess for core to ambient gradient.
1.1vcore, 6x300, stock cooler-------------------same settings but water+PA120.3
ambient 24C------------------------------------------------ambient 24C
IHS 30C----------------------------------------------------IHS should be 27C (b/c cpu set to track IHS at idle)
CPU diode 30C (reads few C too low at idle)--------------CPU diode reading 27C (set track IHS at idle not load)
core temp 34-35C (best guess)---------------------------core temp 30-31C (best guess)
Using water or top air cooling ~6-7C difference between core temp and ambient temp
when undervolted, underclocked idle. It can not be less than 5C, can not be more than 8C.
IHS is 3 C above ambient. Gradient from IHS to core estimated 3 ways. One is by checking temps at same settings in 4 diff ambients,
then plotting error backwards came out to 30.5C, going by 2C error at higher temps came out to 31C, and using known gradient of 4C on pentium and 4-5C heatsink off E8400 and knowing should be less with heatsink on 30-31C.
Using water/PA120.3 stock 6x333 (speedstep enabled), stock volts 1.2v core, idle, core temp is ~7-8C above ambient.
Using stock intel cooling, undervolted, underclocked likely 10-11C gradient from ambient to core, as IHS is 6C above ambient and core another 4-5C (at least) above IHS, gradient cant be less than 9, cant be more than 12C.
Using stock intel cooling, stock clock, stock volts 1.2vcore, gradient from ambient to core about 14C. (the higher the voltage you go, the more benefit you see from better cooling)
when choosing cpu temp calibration for E8400, apparently need to decide:
1) do you want your cpu temp to report the temp where the cpu diode is located, between cores, and report a few C cooler than die temps on load
or 2) do you want your cpu temp to approximate IHS temp and report 14C cooler than die temps on orthos load or up to 26-28C cooler temps on max linpack load (assuming stock settings, stock intel cooling on (E8400) ie....tjmax 100C - tcasemax 72C....ie it is not possible to actually track true IHS temps with cpu diode, because it is located in wrong place and calibration would need to be adjusted by 20C going from idle to max load. So do choice 1, choice 2 is not possible....it can be calibrated to mimic IHS idle OR IHS orthos load OR IHS linpack load, but one of the three will be accurate the other two would be wildly off.
In previous intel docs and even in recent slides, intel states DTS is calibrated such that throttling occurs just above tcase max...ie when cpu at full load that produces near 100C tjmax temps, at intel worst case testing parameters, IHS temp should be just over 72C...assuming intel testing parameters, stock clock, stock cooling, intel loading program etc. Who knows the exact relationship when OCing, I could not really test it as already at 83C with linpack on intel cooler.
Interestingly the GB bios calibrates cpu temp 7C lower than what I have it set to (bios F7)...so cpu temp reads -7C from true IHS at idle, +7C over true IHS at orthos load, and ~+20C too high at linpack load....they split the difference between idle and orthos load, which is probably the best you can do if trying to mimic IHS.
In the pics, prior to drilling a hole in intel stock cooler, I tried with native fan, stock settings, idle and load. I then placed a box fan to hit intel heatsink and removed intel fan and put box fan on a speed to replicate same temps, since I could not use fan with thermocouple attached. After drilling hole in heatsink, I got roughly same temps within 1-2C...so one little hole did not affect things too much.
Also in last pic, note after load is off, immediately IHS temp is within 8C of core temp, and tracked within 7-8C of core temps back down several degrees, suggesting 5-6C difference between IHS temp and true core temp at idle at stock settings with speedstep on using crappy intel cooler...can not be more than 8C and core temp is reading 2-3C too high at that point, so should be 5-6C.
so at idle, gradient between tcase & tjunction is ~ 2 to 5 Celcius? And as you go into loaded temperatures, the cpu maxes out at 72C tcase & 100C tjunction and the gradient increases to ~ 27C.
Temp #1 COOL Idle (sensors probably stuck - evident by testing outside)
Tcase:29C
Tjunction:30C
Cpu Temp:35C or 41C(wrong)
Tcase/Tjunction Gradient:~1C
Tcase/Cputemp Gradient:5C or 11C(wrong)
Temp #2 MILD temps
Tcase:47.4C
Tjunction:65C
Cpu Temp:~61C
Tcase/Tjunction Gradient:~18C
Tcase/Cputemp Gradient:~4C
Temp #3 HOT~84C coretemp
Tcase:56.7C
Tjunction:84C
Cpu Temp:~80C
Tcase/Tjunction Gradient:~27C
Tcase/Cputemp Gradient:~4C
Temp #4 HOT (Theoretical Max)
Tcase:~72C
Tjunction:~100C
Cpu Temp:~94C?
Tcase/Tjunction Gradient:~27C? (If tests are correct)
Tcase/Cputemp Gradient:~6C?
Temp #5 Cool down to idle
Tcase:50.2C
Tjunction:58C
Cpu Temp:55C?
Tcase/Tjunction Gradient:~8C
Tcase/Cputemp Gradient:~5C?
Interesting. This means that when you're running your E8400 at 80C core temperature you're nowhere near intels Tcase maximum or 72.4 or 74.1C. You're probably closer to 58-60C Tcase.
Thanks for the tests Rge!
one last pic showing IR vs thermocouple...turning computer on then off, both showed 44C, then tracked down within 1C of each other to both reading 37 in pic...took some pics where both read ~83C...but did not come out.
so your IR thermometer is/was correct from the start and the thermocouple is not actually needed? Interesting! Am I correct in guessing that the Tcase to Tjunction gradient is increasing as the junction temperature rises from 40C --> 90C?
For example:p::
Tcase temp: 30 40 45 50 55 60 65 70 74
Tjunct temp: 31 42 50 58 66 76 84 95 100
Gradient ~: .01...2...5...8..11.16.19..25.27
Is this a close scale?
yes, assuming full load, stock cooler, stock vcore, stock clock, exact intel loading program, and reasonable ambients. Intel states under those conditions, throttling is set to occur (tjmax reached) just as tcase is exceeded. Also depending on type loading program that gradient can vary significantly even at same temp, which is why intel goes on to say in docs that the relationship is not guaranteed.
And of course if you cheat and remove cooler to get temps that high at idle, then relationship no longer true and tcase = tjmax - 5C. When overclocking and different cooling, I am sure significant gradient exists...but likely different in some ways...just dont know how much.
Also in your other post, under Temp #1 you switched temps on cpu and junction, also my cpu temp reads 2-3 too low at idle temps, and I think you meant to say Tjunction/cpu gradient instead of Tcase/cpu gradient at end of each...but thanks for summarizing, saved me some typing:D
It's me again with yet another insane idea. :)
First of all : rge, you rock! :clap:
Now back to the idea. As we know Intel might mean different things with their new Target TJ value. It seems obvious that those 70C & 80C for 65nm mean something different than 95-100C for 45nm despite being given the same name. But, as rge has proved, at DTS=0 we are supposed to get IHS temps very close or equal to those listed in thermal specification (72-74C for 45nm CPUs). But personally I cannot believe in a gradient of 27C (or maybe even more, as it will most likely increase with higher temps) between core temps and IHS. The previous P4 testing is a good proof to that. On a 65nm CPU this gradient would've been much lesser and much more reasonable, should we decide to use Intel's TJ Target value of 70C for B2 or 80C for G0 (15-20C offset from guessed TJmax used earlier) and IHS values taken from processorfinder of 60.1C and 72C respectively. So maybe these new "official" numbers for 65nm aren't that wrong? Thermal specification for 45nm is very close to that of 65nm G0 stepping (72-74 vs 72). If we (hypothetically) assume TJmax=80C (same 20C offset) for 45nm CPUs then we'd see only 7C gradient in rge's testing and 6-8C gradient at DTS=0 according to Intel's specs (72-74 IHS temps and this hypothetical 80C Tjmax). The abnormally low core temperatures in this case at idle & medium load could be explained by sensors' inaccuracy (slope error) while high load core temps would be more accurate & close to IHS temps.
Sorry for my English, I'm not sure I expressed everything the way I meant to.:D
I am now positive there is a 27C gradient from tcasemax to tjmax at full load (high TDP), measuring at true IHS versus core. Note this has nothing to do with the small few C gradient from DTS die temps to cpu diode (between cores still in die with very high thermal conductance). But to see this gradient from IHS to core temps you have to be at full load (high TDP) with a heatsink. A large gradient was duplicated at university testing better than mine on Pentium northwood.
If I remove heatsink, at idle, low volts, (LOW TDP) when tjmax of 100C is reached IHS thermocouple reads 95C, because there is no load (minimal TDP) to drive a gradient, so no gradient exists other than minimal across tim1.
Putting heatsink on to cool IHS, placing a load to drive the gradient and the higher the TDP, the higher the gradient given same type of load and other parameters, and you can measure a 27C gradient from IHS to core temp at max TDP. The P4 has same gradient if you test with heatsink on...I tested with heatsink off.
Intel states even in recent slide presentation
"DTS calibration point adjusted higher than target TJUNCTION
– Minimizes potential for PROCHOT# activation below TCASEMAX"
So intel cpu under stock conditions, under max TDP load is designed for throttling DTS=0 at just above tcasemax....to self protect cpu, assuming you do not cheat and raise temps at low TDP by removing heatsink.
If you use tjmax 80 for E8400, than you would have trouble explaining why when IHS temp reads 94C, distance to tjmax is 1 and it is not throttling.... so it is not possible for E8400 tjmax to be less than 95C, nor is it possible to have 100 tjmax with more than 1C DTS sensor offset (effectively same thing as lowering tjmax). Given 4-5C gradient at idle, it has to be 99 to 100C.
That's true.
Then maybe DTS data depends on TDP too? And DTS reports accurate temps only when testing with a cooler, not without & undervolted, underclocked? In that case I would still like TJtarget = 80C.
Under stock conditions we're supposed to get TCasemax at target TJunction (DTS=0). Your testing proved that. At DTS=0 it starts throttling and tries to keep the temperature at or below target TJunction (and TCasemax, since they're equal at stock conditions).
Some Intel datasheet (found the quote here) says:
"...In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum TC..." Or above target TJunction which is the same.
Once again those 20C...
What if:
- PROCHOT# is triggered at TJtarget which as we know is DTS=0 (throttling starts)
- THERMTRIP# is triggered at TJmax which is... DTS=-20 and the absolute maximum temp (CPU shuts itself down)
- the 100C value for 45nm processors in the August pdf is the TJmax value (it was even called so at that time), and not the TJtarget
- the 80C value for G0 65nm processors (with same TCasemax temps as for 45nm ones!) is the TJtarget value and TJmax is the same 80+20=100C but occuring not at DTS=0 but at DTS=-20
- the target TJunction in October pdf means a) a "real" TJtarget for 65nm CPUs b) the good old yet misunderstood TJmax for 45nm CPUs (while "real" TJtarget being the same 80C). Maybe they didn't dare to change it since they already published 100C before in August (then why not use TJmax for other CPUs? - still a mystery)
For me it's the only way of explaining why Target TJunction values for 65nm and 45nm processors differ so much when their TCasemax temps are equal.
P. S. It's only my version. You guys must know much more than I do, so please forgive me this nonsense I wrote. :)
The temp sensor is going to function and report temps the same whether heat sink is on or off, TDP will not affect DTS functioning. My E8400 shuts off at around 115-118C tcase, it throttles at 95C tcase...so again not possible for tj 80C on e8400.
If you are having trouble believing 28C gradients exist over such a small space...read this research paper of pentium northwood....look at slide 22. Gradients exist that high on E8400 as well, but primarily because of more optimal sensor placement of die sensors and diode sensors and copper banding in silicon die, die shrinkage, etc the gradient will not be seen from dts to cpu diode, but from those two diodes to IHS.
http://www.ee.ucr.edu/~stan/papers/todaes07_softsen.pdf
LINKS TO YOUTUBE VIDEOS BELOW SHOWING GRADIENTS
According to intel Tcase formula
Tjmax-Tcasemax gradient = theta(jt)*TDP
The higher the TDP the higher the gradient from Tj to Tcase. TDP is primarily dependent on load but also voltage, however core temps in themselves dont alter the gradient...just that under normal circumstance temps are only high at high loads. See formula in pic below.
Though you will never see this gradient, unless you measure tcase with thermocouple...as gradient from core to cpu temp is not more than 5C.
At 1V, IDLE ie LOW TDP, 2x266, there is a 5C gradient from tjmax to tcase whether temp is 60C or up to 100 C (no heatsink). ie, at 100C core IHS = 95C... or at 50C core IHS=45c, etc. (at lower core temps gradient is still 5C, but reads 10C from DTS reading 5C too high in idle range)
At 1.25v, IDLE, 9x333, there is a 7C gradient from tjmax to tcase regardless of temp, 60C to 100C, (slightly higher TDP as higher vcore)
ie at 100C tjunction IHS=93...or at 50C tjunction, IHS=43C, etc (at lower temps gradient still 7C reads higher from inaccurate DTS in low range)
At 1.4v, idle 9x333, there is a gradient from tjmax to tcase of ~10C from 60C to 100C (again higher idle TDP from higher vcore)
ie at 100C tjunction, tcase is 90-91, etc
Stock cooler, stock 9x333, 1.25 vcore
idle, gradient core to IHS = 6-7C
orthos load 14-16C
linpack load 22-24C
load at higher volts increases gradient, better cooling decreases gradient.
Video 1 demonstrates high temps with low TDP (IDLE) using 1.37 vcore (so temps would get higher) illustrates still only 9-10C whether temps are in low range or high range...only showed high range, point being gradient is TDP dependent, not temp dependent.
http://www.youtube.com/user/rge42
Video 2 demonstrates first intel cooler w/box fan, stock vcore 1.2, stock 9x333, idle (low) TDP, with 6-7C gradient (gradient reads 1-2C too high as 1-2C DTS error in that range. Then linpack load demonstrating 22-23C core to IHS gradient, then slightly higher gradient as decrease fan speed and lessen cooling ability.
http://www.youtube.com/watch?v=q7ua2FFByfI
I am done with testing for awhile...2:30 am...need to sleep. If anyone wants to duplicate experiment, just get thermocouple calibrated for surface temps (calibrated 4C higher per eng i borrowed from). drill small notch dead center in IHS very shallow depth to just seat tip of thermocouple, put small amount of thermal grease on tip...but to use second method to guage temps, mine were within 1C of IR temps, I duplicated approximate depth for tcase measurement per intel...though the notch did not alter temps but maybe .5 to 1C, it did however make them very reproducible within 1-2C.
This is all very interesting theoretical stuff, but I'm not seeing what relevance it has to making RealTemp, which only reads the DTS info from the chip and doesn't read temps at all, more accurate in reporting the actual chip temperature. Other than at low-end calibration, how does any of this information or speculation help? Is it changing the top point of the graph in any meaningful way?
I thought the only practical value of note was the TjMax one, which is what RealTemp uses to convert the DTS to a temp reading. How is Tcase or anything else useful? Once I've put a heatsink on my chip, I don't give a flying f* what temperature the IHS or the heatsink is at, as long as it's keeping the processor cool... :shrug:
I'm just wondering how this information will help us get a better value for TjMax? Short of us all drilling holes in our CPUs to calibrate each one accurately, I thought we were all stuck with the +/-20 degree inaccuracy inherent in these sensors and in the original per-chip Intel calibration. To a casual onlooker, it seems we are pretty much back to square one right now, to what unclewebb was saying about a year ago in threads here, that the only useful info is the DTS reported distance from TjMax and that as long as you're not throttling you shouldn't really care too much. :ROTF:
Kevin (Unclewebb) had asked me if I could find a way to measure the IHS temp via a thermocouple for the purpose of gradients and resting idle temps, which is useful to determine idle temp calibration as well as trying to figure out tjunction diff between 65nm and 45nm, hence get accurate load temps as well. Also understanding the gradients helps with understanding Tcase specs. If all you are interested in is distance to tjmax, then yes this information is useless. But if it upsets you in some way for those of us interested in absolute temps, why not just ignore it, instead of needing to post you dont give a "flying f" about it?
Well Intel lets you know that you can't get the chip hotter than ~ 73C Tcase, but the software only measures DTS (Tjunction). The purpose is to find the exact relationship between Tcase and Tjunction (the gradient).
You know you can't run your E8xxx/E7xxx hotter than Tjunction = 100C, but how do you know your Tcase temperature at that point?
This is the reason for measuring the temperature on the IHS.:up:
Thanks...IHS temp has a few seconds lag for heating up since it is being cooled, but the gradient then stays constant ~20-24C (expect when linpack drops off between intermittent loads). If you watch as IHS is climbing after initial several seconds of equilibration.. .1, .2 as soon as it gets 1C hotter, realtemp core gets 1C hotter...so if temps start out tcase 55, core 77...when tcase gradually increases to a steady state, case temp was 65 and core 87 with fan on medium. I have several hours of testing and couple hours of video ...most would make you puke to watch from motion sickness....had to learn how to video. Also I turned fan speed down at end to show gradient increases couple degrees with worse cooling.
Yes, thanks rge. Your testing is detailed and useful as always. :clap: The info on Northwood temp calculations was also very educational. :yepp:
I must admit you beat me. But then we just have to admit that Target TJ values for 65nm are plain wrong... Or Intel means something else with these new numbers. :shrug:
P.S. The thermal specification formula is quite interesting too. It could explain why newer steppings have higher TCasemax temps (relative to their TJunction temps). If the psi (or theta?) value is a constant, then due to lower power consumption (TDP) of the new stepping we get less difference (gradient) between TCasemax & TJunction. This makes me think that TCasemax might be some kind of "secondary" value, calculated (or measured) based on TJunction temperatures, as it isn't a whole number.
So, in conclusion, the maximum core temperatures for C0 and E0 E8xxx series chips is......
:p: