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Originally Posted by mesyn191
The bandwidth difference has nothing to do with the L2 cache itself, the bus on the K8 is 128 bit vs. Intels 256 bit bus. That is all there is to it...
Intel's L2 cache is denser, more efficient, has better prefetchers, a lower miss rate and double the bandwidth thanks to the 256bit bus. Arguing that the cache is the same and only the bus differs is an excercise in semantics.
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I'm sorry but you're gonna have to post links backing this up that is true vs. what AMD has right now (ie. P4...). Everything I've heard suggests thier prefetching is pretty good as is thier BPU. As good as Conroe's? Probably not, but then its a new arch. so what do you expect? Conroe still aint' out yet, and vs. Netburst what the K8 has had so far has worked pretty damn good, don't you think? So I think calling it "woefully inferior" is making mountains out of mole hills.
I was comparing K8 to Conroe. If you want to fall back on K8 vs P4, be my guest but please don't waste my time.
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Supieror how? For mult. threaded apps sure, a shared cache is better than 2 split L2's but for everything else there is nothing inheritly better about Conroe's cache scheme. Inclusive vs. exclusive is all about saving die space vs. design simplicity BTW.
So you don't think that each core having use of the entire cache is an advantage for single-threaded apps or multi-tasking?
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I'm sorry but this is totally wrong, or at the very least highly speculative that all code will be limited by L2 bandwidth. Most code is dependant on latency instead of bandwidth as it is highly random in nature...
What's wrong? I never said that all code was limited by L2 bandwidth.
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I would disagree, AMD's problem with the K8 currently is with the decoders, not L2 bandwidth. Whats the point of having a high bandwidth L2 if the core can't make use of it since its waiting for instructions to be decoded most of the time right?
Good point.
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Now with K8L that will change, the effectively single cycle SSE2 FPU that it'll have WILL require lots of L2 bandwidth to make proper use of, and in that instance AMD might indeed be limited by thier L2 in situations that stream lots of SSE2 FP code. Right now though the L2 is fine, only thing they'd have to do is modify thier ODMC and supporting hardware in the CPU to support a shared L2 (or as in K8L's case, a shared L3) and it'd be on par with what Conroe has to offer as far as the mem. subsystem goes.