AMD new E6 revision replaces E3 one's

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06-08-2005, 11:43 PM
Ratax

AMD new E6 revision replaces E3 one's

" Model numbers 3800+, 3500+, 3200+ and 3000+ in socket 939 only will be affected by the new revision change from E3 to E6.

The E6 revision is pin to pin compatible with the current E3 revision, and will function in existing platforms based on 939 pin AMD Athlon(tm) 64 processors, but a new BIOS will be required to recognize the new CPU ID (Current CPU ID will change from 00020FC0h to 00020FC2h).

This new revision is expected to start shipping from July 15th 2005 and the marking of the affected model numbers will change as shown below:

MODEL NUMBER PREVIOUS PIB REF NEW PIB REF
3800+ ADA3800BPBOX ADA3800BWBOX
3500+ ADA3500BPBOX ADA3500BWBOX
3200+ ADA3200BPBOX ADA3200BWBOX
3000+ ADA3000BPBOX ADA3000BWBOX
"
Source: AMD email.

There will be new E6 revisions in socket754 models too.
The mail doesn't says about changes in this E6 revision.
06-08-2005, 11:48 PM
OC Detective

Does that not mean that if a mobo supports the new E6 single core then it must also support the E6 dual core too which by extrapolation means that any mobo that supports E3 will support E6 dual core?
Your source is named as "AMD email" - I assume then it is 100% legit.
06-09-2005, 12:20 AM
frostedflakes

So wait, E6 is the dual core revision, correct?

Why are the single-core Venice going to be using these? Is AMD planning to sell X2s with a failed core as Venice (similar to the 512KB Clawhammers on S754 and S939)?
06-09-2005, 12:23 AM
hitmanx2

will they be better overclockers? :slobber:
06-09-2005, 12:25 AM
Fairydust

Even more important, what is a fitting nickname for the Toledos?

Going from San Diego's Sandy to Toly? No that doesn't sound good, so Tod Toledo, Ted Toledo, hmm yeah Teds are nice people :P let's call it Ted(d)y.
06-09-2005, 12:40 AM
OC Detective

Quote:

Originally Posted by frostedflakes

So wait, E6 is the dual core revision, correct?

Why are the single-core Venice going to be using these? Is AMD planning to sell X2s with a failed core as Venice (similar to the 512KB Clawhammers on S754 and S939)?

I guess that is possible, streamlines the process optimises output and the core size is similar to a 130nm Newcastle anyway.
06-09-2005, 12:51 AM
SIOUX

Quote:

Originally Posted by Fairydust

Even more important, what is a fitting nickname for the Toledos?

Going from San Diego's Sandy to Toly? No that doesn't sound good, so Tod Toledo, Ted Toledo, hmm yeah Teds are nice people :P let's call it Ted(d)y.

Mad man :D :D
06-09-2005, 01:47 AM
EvilWhiteDragon

Quote:

Originally Posted by Fairydust

Even more important, what is a fitting nickname for the Toledos?

Going from San Diego's Sandy to Toly? No that doesn't sound good, so Tod Toledo, Ted Toledo, hmm yeah Teds are nice people :P let's call it Ted(d)y.

I think we should call them Do's, Toledo's
06-09-2005, 01:52 AM
Gorod

Quote:

Originally Posted by hitmanx2

will they be better overclockers? :slobber:

I wonder the same thing :toast: , it is time to sell E3's and prepare for E6 ? :eek: :D
06-09-2005, 02:04 AM
Fairydust

Quote:

Originally Posted by EvilWhiteDragon

I think we should call them Do's, Toledo's

No way, this breaks the unwritten rule "Thou shalt use at least the first letter of the word which is to be abbreviated."
:fact:
06-09-2005, 02:16 AM
STEvil

wonder if you could enable the second core if its there..
06-09-2005, 02:16 AM
dimasdw

Quote:

Originally Posted by Ratax

MODEL NUMBER PREVIOUS PIB REF NEW PIB REF
3800+ ADA3800BPBOX ADA3800BWBOX
3500+ ADA3500BPBOX ADA3500BWBOX
3200+ ADA3200BPBOX ADA3200BWBOX
3000+ ADA3000BPBOX ADA3000BWBOX

BP is venice and what is BW ?
maybe we can call Toledo, TODO or TOLE :D
06-09-2005, 02:18 AM
dimasdw

Quote:

Originally Posted by STEvil

wonder if you could enable the second core if its there..

enable the second core with pencil trick :D
06-09-2005, 02:21 AM
Davos

so why have they brought this out?? will it overclock better??
06-09-2005, 02:31 AM
STEvil

BP is E3
BW is E6

for those who didnt catch on.
06-09-2005, 02:41 AM
mad mikee

Hey what happened to the BSBOX?

Sorry just woke up and could resist since someone already came up w/ rev6 = todo :D
06-09-2005, 02:59 AM
s7e9h3n

Quote:

Originally Posted by STEvil

BP is E3
BW is E6

for those who didnt catch on.

Then what's BV? BTW, I think TULLY would be appropriate ;)
http://img264.echo.cx/img264/9143/4600x26wc.jpg
http://img193.echo.cx/img193/3263/3300cpuz1zw.jpg
06-09-2005, 03:07 AM
bugeyes

Quote:

Originally Posted by LOE

probably failed dualcore - e3 + e3 = e6

Wrong... e3 + e3 = 2e3 ;)
06-09-2005, 03:48 AM
dimasdw

@s7e9h3n

BV is Manchester 512 kb L2 Cache
and CD is Toledo 1 Mb L2 Cache
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?
06-09-2005, 05:16 AM
Davos

Quote:

Wrong... e3 + e3 = 2e3 hmm but e3 is the same as 3e

e3 can also be written as 3e

3e + 3e = 6e :)

but if it was e³ + e³ then it would be 2e³ :D

:off: soz
06-09-2005, 06:27 AM
mongoled

Quote:

Originally Posted by bugeyes

Wrong... e3 + e3 = 2e3 ;)

Nice, had me chuckling there

:)
06-09-2005, 07:26 AM
Crosis

I would like to how they will be o/cin' according to Venice...
06-09-2005, 07:43 AM
eva2000

Quote:

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo :D
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

:slobber: :slobber: :slobber:

That yours ? :)
06-09-2005, 08:07 AM
s7e9h3n

Quote:

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo :D
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

Gee thanks :rolleyes: , I know it may be hard to believe, but you can't always trust cpu-z's ID's. This is the exact same cpu as above (I sent it to OPB):
http://www.ocxtreme.org/onepagebook/.../pcmk0494k.jpg
06-09-2005, 08:17 AM
situman

so E6 revision chips are still dual channel? Its just a failed dual core?
06-09-2005, 09:03 AM
panumas05

E6 in Dual core.

http://www.xbitlabs.com/articles/cpu...on64-x2_3.html

But new BW is disable Dual core and disable cache ?
06-09-2005, 10:01 AM
metro.cl

weird anyone can tell more???
06-09-2005, 10:17 AM
setyotomo

@s7e9v3n : 9476 PC Marks :banana:
06-09-2005, 10:57 AM
[XC] leviathan18

i dont think disable core disable cache is more likely to be faulty core or cache
06-09-2005, 11:03 AM
terrace215

Quote:

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo :D
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

BV is used for Manchester (2 x 512K L2)
CD is used for Toledo (2 x 1MB L2)

And, BTW, clearly, AMD is not going to use 2 x 1MB L2 die for Venice (1 x 512K L2) parts.

So, more than 1 die (cache size, etc) can use the same "E6" stepping.

For a while I thought AMD was using the #s just to differentiate dies, with E3, E4 and E6 all being the same "E" stepping, but if this email is correct, that is clearly not the case.
06-09-2005, 11:43 AM
_Eduard_

I can't wait for E6 sempr0ns :D
06-09-2005, 12:10 PM
Quanticles

Quote:

Originally Posted by Davos

e3 can also be written as 3e

3e + 3e = 6e :)

but if it was e³ + e³ then it would be 2e³ :D

:off: soz

e3 is a variable name though, you cant have it start with a number =P
06-09-2005, 01:21 PM
s7e9h3n

Quote:

Originally Posted by setyotomo

@s7e9v3n : 9476 PC Marks :banana:

That's not my work, it's OPB's with the cpu he got from me... ;)
06-09-2005, 03:07 PM
dimasdw

Quote:

Originally Posted by eva2000

:slobber: :slobber: :slobber:

That yours ? :)

no,thats picture from a Hardware website :D
06-09-2005, 03:31 PM
dimasdw

Quote:

Originally Posted by terrace215

BV is used for Manchester (2 x 512K L2)
CD is used for Toledo (2 x 1MB L2)

oh sory I am Wrong,your right ....
I forgot where i read about denmark and Toledo

Link
<translate with http://world.altavista.com/babelfish/tr> :D
06-09-2005, 05:56 PM
Borgschulze

Quote:

Originally Posted by s7e9h3n

Then what's BV? BTW, I think TULLY would be appropriate ;)

Hey, how about we call them...
TOLEDO!
06-09-2005, 09:17 PM
CNCL

Wait, I am lost. Is the new E6 venice/SD core?
06-09-2005, 10:03 PM
OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.
06-09-2005, 10:04 PM
TMM

Could just be a minor core revision...
:stick:
like the Clawhammer C0 and CG...

Maybe the Venices (if E6 = Venice) will finally have a decent Mem controller :toast:
06-10-2005, 12:42 AM
Fairydust

Quote:

Originally Posted by OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

Correct me if I am wrong, but according to AMD, the 1 Mb version is the E6 and the 512 Kb is the E4
06-10-2005, 12:53 AM
Lithan

Quote:

Originally Posted by dimasdw

BP is venice and what is BW ?
maybe we can call Toledo, TODO or TOLE :D

Bout time someone got it right.

Let my provlaimation go across the land!
They wil be known as Todos!
06-10-2005, 01:05 AM
Fairydust

But teddies are cute and fluffy. Todos are mean and smelly. so we got Todos, Tully and Teddy now?
06-10-2005, 01:17 AM
AgentVX

Quote:

Originally Posted by OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

Then we should call the dual core one Man United and the single core one will be Man City :ROTF:
(English football joke)
06-10-2005, 01:22 AM
shuRe

winchester = winny

san diego = sandy

toledo = toley, or TROLLEY :cheer:
06-10-2005, 08:04 AM
The Coolest

The AMD K8 0.13µm Hammers were SH7-B3, SH7-C0, SH7-CG, there was also a DH7-CG.
the SH7s were Sledgehammers and Clawhammers, the DH7 was a NewCastle.
The first gen of AMD's K8 0.09µm Hammers were DH8-D0 and SH8-D0.
SH = 1MB
DH = 512KB
7 = 0.13µm
8 = 0.09µm
9 = 0.09µm Dual Core
Its very confusing lately as AMD isn't saying what type any of the E stepping hammers are.
But I'm guessing that the new E6 sempron is going to be a DH8-E6, the current Dual cores are *probably* DH9-E4 for DC 2x512KB and SH9-E6 for 1x1MB
06-10-2005, 04:20 PM
dinos22

E6 we're there dude :woot:

:gay: ...i know man......winnie, sandy, teddy....WTF....

Quote:

Originally Posted by LOE

does every amd core need to have a :banana::banana::banana:got name?
06-10-2005, 04:27 PM
s7e9h3n

Quote:

Originally Posted by The Coolest

The AMD K8 0.13µm Hammers were SH7-B3, SH7-C0, SH7-CG, there was also a DH7-CG.
the SH7s were Sledgehammers and Clawhammers, the DH7 was a NewCastle.
The first gen of AMD's K8 0.09µm Hammers were DH8-D0 and SH8-D0.
SH = 1MB
DH = 512KB
7 = 0.13µm
8 = 0.09µm
9 = 0.09µm Dual Core
Its very confusing lately as AMD isn't saying what type any of the E stepping hammers are.
But I'm guessing that the new E6 sempron is going to be a DH8-E6, the current Dual cores are *probably* DH9-E4 for DC 2x512KB and SH9-E6 for 1x1MB

http://img292.echo.cx/img292/7599/opbcpuz1292zw.jpg
06-10-2005, 04:38 PM
The Coolest

i'm in contact with CPUz author, and I'm not sure whether its a DH or SH yet, but it sure is a 9-E4. Actually I think I gave him the info on the codes for these chips..
06-10-2005, 04:53 PM
ArcTan

Quote:

Originally Posted by dinos22

E6 we're there dude :woot:

:gay: ...i know man......winnie, sandy, teddy....WTF....

winnie and sandy sound like girl names
thats what it should be :D
06-10-2005, 05:02 PM
Cooper

Haven`t you guys noticed that Sempron E6 has the same CPUID as Sempron 64 ???
06-10-2005, 05:08 PM
The Coolest

Sempron E6 IS a Sempron with 64bit extentions
06-10-2005, 05:18 PM
dinos22

good point......well then Venice is babyelf's Petra

Quote:

Originally Posted by ArcTan

winnie and sandy sound like girl names
thats what it should be :D
06-11-2005, 12:34 AM
Highland3r

So E6 revision, is that dual core's? Or as TMM mentioned earlier simply a revision of the current E3 core?
ie, if you brought an E6 stepped 3000, would this be a dual cored chip, with 1 core /1/2 the cache disabled?
06-11-2005, 01:30 AM
The Coolest

Quote:

Originally Posted by Highland3r

So E6 revision, is that dual core's? Or as TMM mentioned earlier simply a revision of the current E3 core?
ie, if you brought an E6 stepped 3000, would this be a dual cored chip, with 1 core /1/2 the cache disabled?

Quote:

Originally Posted by The Coolest

The AMD K8 0.13µm Hammers were SH7-B3, SH7-C0, SH7-CG, there was also a DH7-CG.
the SH7s were Sledgehammers and Clawhammers, the DH7 was a NewCastle.
The first gen of AMD's K8 0.09µm Hammers were DH8-D0 (Winchester) and SH8-D0 (Unknown code name).
SH = 1MB
DH = 512KB
7 = 0.13µm
8 = 0.09µm
9 = 0.09µm Dual Core
Its very confusing lately as AMD isn't saying what type any of the E stepping hammers are.
But I'm guessing that the new E6 sempron is going to be a DH8-E6, the current Dual cores are *probably* DH9-E4 for DC 2x512KB and SH9-E6 for 1x1MB

Its a new revision of the DH8-E3 (Venice)
06-11-2005, 02:55 PM
VVJ

Quote:

Originally Posted by Ratax

"The E6 revision is pin to pin compatible with the current E3 revision, and will function in existing platforms based on 939 pin AMD Athlon(tm) 64 processors, but a new BIOS will be required to recognize the new CPU ID (Current CPU ID will change from 00020FC0h to 00020FC2h)."

Wrong! According to my source in AMD Inc. CPUID of Athlon 64 will change from 20FF0h to 20FF2h! Besides, Sempron will get CPUID of 20FF2h as well as 20FC2h.
06-11-2005, 03:02 PM
The Coolest

20FC2 = s754 E6
20FF2 = s939 E6
VVJ: is it DH8-E6?
also this means it going to be a cut down E6 Venice

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