AMD to disclose their 32nm tech...
...and enhancements made to AMD’s x86 core that will appear in the first Fusion APU (Llano)!
One of the most important events is few weeks away - ISSCC, and it'll bring some exciting disclosures:
5.6 An x86-64 Core Implemented in 32nm SOI CMOS
4:15 PM
R. Jotwani1, S. Sundaram1, S. Kosonocky2, A. Schaefer1, V. Andrade1, G. Constant1, A. Novak1,
S. Naffziger2
AMD, Austin, TX 2AMD, Fort Collins, CO
The 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35
million transistors (excluding L2 cache), operates at frequencies >3GHz. The core incorporates
numerous design and power improvements to enable an operating range of 2.5 to 25W and a zero-power
gated state that make the core well-suited to a broad range of mobile and desktop products.
http://www.isscc.org/isscc/2010/ISSC...nceProgram.pdf
there's also more exciting things:
5.4 The Implementation of POWER7TM: A Highly Parallel and Scalable Multi-Core High-End
Server Processor
3:15 PM
D. Wendel1, R. Kalla2, R. Cargoni2, J. Clables2, J. Friedrich2, J. Kahle2, B. Sinharoy3, W. Starke2,
S. Taylor2, S. Weitzel2, S. G. Chu2, S. Islam2, V. Zyuban4
IBM, Boeblingen, Germany 2IBM, Austin, TX
IBM, Poughkeepsie, NY 4IBM T.J. Watson, Yorktown Heights, NY
POWER7TM the next generation processor of the POWERTM family is introduced. The 8-core chip,
supporting 32 threads, is implemented in 45nm 11M CMOS SOI. The 32kB L1 caches feature 1
read port banked write for the I-cache and 2 read ports banked write for the D-cache. The on-chip
cache hierarchy consists of a 256kB fast, private SRAM L2 and a 32MB shared L3, implemented
in embedded DRAM
+
5.2 A 40nm 16-Core 128-Thread CMT SPARC SoC Processor
2:00 PM
J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson,
F. Schumacher, D. Greenhill, A. Leon, A. Strong
Sun Microsystems, Santa Clara, CA
A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to
maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s
support the required bandwidth. Six clock and four voltage domains, as well as power
management and circuit techniques, optimize performance, power, variability and yield trade-offs
across the 377mm2 die.
And no I'll not skip Intel ;)
5.7 A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS
4:45 PM
J. Howard1, S. Dighe1, Y. Hoskote1, S. Vangal1, D. Finan1, G. Ruhl1, D. Jenkins1, H. Wilson1, N. Borkar1,
G. Schrom1, F. Pailet1, S. Jain2, T. Jacob2, S. Yada2, S. Marella2, P. Salihundam2, V. Erraguntla2,
M. Konow3, M. Riepen3, G. Droege3, J. Lindemann3, M. Gries3, T. Apel3, K. Henriss3, T. Lund-Larsen3,
S. Steibl3, S. Borkar1, V. De1, R. Van Der Wijngaart4, T. Mattson5
Intel, Hillsboro, OR 2Intel, Bangalore, India 3Intel, Braunschweig, Germany
Intel, Santa Clara, CA 5Intel, DuPont, WA
A 567mm2 processor on 45nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6×4 2D-mesh
network. Cores communicate through message passing using 384KB of on-die shared memory. Finegrain
power management takes advantage of 8 voltage and 28 frequency islands to allow independent
DVFS of cores and mesh. As performance scales, the processor dissipates between 25W and 125W.
IMHO this is more exciting than Fermi deep dive! But that's just me!
One thought for contemplating: Llano's CPU part w/0 cache will be 38.76 mm^2 in QC configuration! If we'd be generous and say that L2 is of the same size, that would put CPU part of the die under 80 mm^2!! (more than twice smaller than Propus!)
Also consider that Redwood's 40nm die size is 104 mm^, and feel free to speculate about Llano size! ;)
P.S
just for bragging right none of mainstream news site that we link here didn't write about this yet! ;)
This time around XS is source of info! :up:
