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Bulldozer samples in 2010:Quote:
Originally Posted by fellix_bg
http://img121.imageshack.us/img121/8...tdayrickbe.jpg
presentation from Chekib Akrout, General Manager, Technology Group could be very interesting: http://phx.corporate-ir.net/External...xUeXBlPTM=&t=1Quote:
Originally Posted by informal
Quote:
Originally Posted by Smartidiot89
Quote:
Originally Posted by informal
Quote:
Originally Posted by w0mbat
Quote:
Originally Posted by Face
So, Bobcat is for taking on Atom and such?
Yeah, its a low-pwer CPU design. And it looks very promising!
Yes ,it is very low power but keeping the mainstream performance of today's CPUs. They mentioned sub 1W power draw(idle i suppose),and pretty high OoO performance(citing "90% of today's mainstream performance levels" probably meaning athlon II),so Atom will be fighting a much faster per clock and per Watt cores,but also Atom will evolve by the time ontario cores launch.
Q&A: SOI 32nm for GPU is not "a big issue" and doesn't require major redesign for Llano production. 32nm Llano comes first.BD and Bobcat are same underlying design but developed by 2 separate teams. Bobcat uses one of the BD cores(modules) and is optimized for low power and APU integration.
edit: APU products will be refined on year basis-a bit on CPU and/or GPU side,but the new Fusion design will have a more aggressive roadmap compared to previous CPU roadmaps.
Atom, and most importantly ARM:cool:Quote:
Originally Posted by Aerwidh
wow. lol looks like AMD have been busy little beavers behind the scene. :D
it would be overoptimistic trying to fit x86 power needs in head-2-head fight with ARM... Intel can't do that with In-order Atom, so I don't see how can it be achieved with OoO CPU... and I'm not talking about idle power...Quote:
Originally Posted by Smartidiot89
ARM with GloFo's low power 28nm tech will be unchallengeable when it comes to power, and vastness of ARM market can cover more expensive specialized production technology.
Is this what he said to the question somebody asked about what has been taped out? My psis poor sattelite internet (xplornet) couldn't keep up to the stream set to 50k.Quote:
Originally Posted by informal
[edit]
Also, about the cores. So each core in the new architecture is called a "Bulldozer" core, while products such as Zambezi will be cpu's made up of individual "Bulldozer" cores? That's the way i'm reading it. And "Bobcat" is a completely different core than "Bulldozer", is that correct?
I noticed that they mentioned Bobcat and BD are designed for the around the same ISA... yet the Bobcat slide only mentions SSE1-3, when Bulldozer should be SSE1-4+... So that can't be an absolute statement, as I wouldn't imagine them trying to include all of the latest extensions in Bobcat, to keep core size/power down.
Did they specifically say that Bobcat shares any pieces with BD? They said the whole two separate teams with different design points, but I don't remember them saying anything about how much implementation they shared.
Since one of Bobcat's design points is being synthesize-able, I wonder how much they're positioning it to compete with Intel's Atom. I assume AMD won't be able to license out the cores (for SoCs) to other companies like Intel will be doing at TSMC :X
No, someone asked specifically about the fact that the Fusion chips will be the first time a GPU has been on SOI and if there are any challenges I believe. They dodged the question about what has been taped out (as they don't release internal milestones) and just pretty much said things are on track for the schedule they've announced.Quote:
Originally Posted by flippin_waffles
Hm, 128-bit SIMD units?Quote:
Originally Posted by Smartidiot89
Intel's Sandy Bridge is already confirmed to have its AVX SIMD as full 256-bit implementation:
http://img257.imageshack.us/img257/8271/sandybridge.jpg
I think the idea is that they can combine the SIMD units to process a 256-bit instruction, or have them process two 128-bit instructions, depending on what's needed.Quote:
Originally Posted by fellix_bg
I find this slide about 32nm tech interesting:Quote:
Originally Posted by Oliverda
http://img692.imageshack.us/img692/5...tdayglobal.jpg
50% better than 45nm! That's awesome considering how good is 45nm tech especially with the latest upgrades that gave us "C3" Phenom II
coming years look exciting.. i guess i cannot not stop buying hehe
lolQuote:
Originally Posted by fellix_bg
But this is 128 bit FMAC. I'm not sure that Bulldozer willn't use YMMs 256 bit.:ROTF:
So, it will be SOI + high-k metal gate + 2nd gen. immersion lithography. Intel doesn't use SOI and they will use the immersion lithography for the first time on 32nm.Quote:
Originally Posted by Nedjo
Well, ARM is even getting into OoO designs now, so it's not just straight power consumption, but the computing power available in a power envelope and core area, since we're heading into more and more integration. With a Fusion concept AMD might have a chance, seeing as that's what ARM offerings have right now, ie. a SoC with a cpu core plus some other accelerators (eg. Nvidia's Tegra or TI's OMAPs). However that'd require a lot of effort to pursue on AMD's part, which I would question them having the resources for at the current time.Quote:
Originally Posted by Nedjo
Variable width when it comes to SIMD units-2 threads per FPU/SIMD cluster,total 256b wide execution. AVX is supported and this news was out a while back(posted by AMD fellow at AMD devcental).Quote:
Originally Posted by Solus Corvus
That's not product improvement, it's some unspecified measure of transistor improvement. Probably related to power/leakage as well, since that would provide the larger number to brag about, and they are finally using metal gates at this node, which helps a lot with leakage.Quote:
Originally Posted by Nedjo
very interesting was talking about Fusion
Per Anand, all the Llano APU ("fusion") stuff in 2011 has Phenom II-based CPU cores.
So, while they will likely have a stronger GPU side, the CPU side will be about 2 generations behind Intel's Sandybridge/Ivybridge.
Bulldozer is high-end desktop and server only (at least in 2011).
don't want to go in to your need to state obvious...Quote:
Originally Posted by terrace215
:rolleyes:
of course it's a measure of transistor improvement! Better transistors -> better CPUs! Yeah?
there are bunch of possible parameters that could be related, but regardless it's good to hear that GloFo has mastered HKMG so wellQuote:
Probably related to power/leakage as well, since that would provide the larger number to brag about, and they are finally using metal gates at this node, which helps a lot with leakage.
pfff Anand! Wouldn't be surprised if you were Anand my dear terrace215 fellow ;)Quote:
Originally Posted by terrace215
Anand just has that unexplainable urge to place Intel in any AMD related article, and if possible at the top:
http://www.anandtech.com/cpuchipsets...oc.aspx?i=3673
http://img689.imageshack.us/img689/9...20102011ro.jpg
:shrug:
No,Brazos platform will have APUs too,and Brazos is bobcat core which in turn is one module from Bulldozer.Bobcat is a 2 CPU core product for ultrathin market,with Atom like power capabilities(they stated super low power, sub 1W cores) and 90% of mainstream CPU of today (in terms of IPC/overall perf.).Quote:
Originally Posted by terrace215
I have no idea how Bobcat based APU will fare against SandyB. but it will have the same x86 ISA capability(AVX 256b) so AMD can opt to make a 4 core option and target some other (mobile) market with it.
I think that is 50% scaling improvements in performance per watt expected over 45nm.Quote:
Originally Posted by Nedjo
PS.: Anand is ridiculous and pathetic...
That is the very first thing I noticed as well, it stuck out like a sore thumb! I glanced at the first page, then jumped straight to the conclusion. And as suspected, it read very much like that intel ad did.Quote:
Originally Posted by Nedjo
Anand is probably not the best source for unbiased AMD related content. ATi, sure, they love 'em. After all intel has said a few times in the past that nv worried them the most. That might have been a bad decision! :D
Sorry for cross thread postings,but we have 3 or 4 threads covering same topic :):
As Charlie reports,bulldozer has taped out(?):
Quote:
Bulldozer has taped out, the earth has moved
More analyst day dirt dug up
by Charlie Demerjian
November 11, 2009
THREE VERY INTERESTING tidbits snuck out in the Q&A session at the AMD analyst day today. It seems that Fusion and the new cores have taped out and are at the fabs.
The new cores were said to begin sampling to OEMs in 2010. When pressed on the timing of tapeouts, one AMD spokesperson said that the fabs were 'running product now'. That means the chips have taped out and the fun is about to begin.
Next up was the process the Fusion cores will be on. The first of them will be made on a silicon-on-insulator (SOI) process, something that makes a lot of sense. It is much easier to port a GPU from bulk silicon to SOI than to do things the other way around. The answer did not preclude bulk silicon variants of Fusion in the future, but since the first generation cores are not made on it, I would not expect that to happen for a while.
The last bit was confirmation of what we have know, or at least have strongly suspected for a while, that the first generation of Fusion products will be a 'stars' core. The optimistic view of this is that AMD is reusing the old K10 variant for time to market reasons. Basically the uncore was done first, and since it is modular, why not use it?
If you are pessimistic, you could see this as the Bulldozer and Bobcat cores being massively late. Given that they were on the roadmap for 45nm and delayed about 2 years ago to 32nm, this has a ring of truth to it. Because it was a planned move, and one that rationalizes a likely untenable earlier schedule, I don't think this is a delay, or even a bad thing. The 'delay' probably avoided another "Barcelona".
In the end, it looks like AMD is on track. 2010 will likely be full of pain, but you can finally see the light at the end of the tunnel. The first of the new parts have taped out, so it is only a matter of time before details start leaking. Then we will know if the grand plan is working, at least on a technical level.S|A
Informal, that statement came from the prodding they got on the fact the Global Foundries chart stated 32nm manufacturing in Q3/4 2010, which they responded by clarifying it refers to mass production, while their development usage is currently offered.
As I've said before, they did their best to dodge the tapeout question... they did quickly blurt out that they've got silicon back... but nothing about which product(s) it may be for.
Yeah,it could be Llano for all we know.The thing is something other than simple test wafers has come out from GloFo.
If anyone doesnt know what a certain codename means, heres the anwser!
Quote:
“Adelaide”
Market: Server
What is it? Ultra low-power server platform for the 1P and 2P markets. “Adelaide” will feature a C32 socket and the low power AMD SR5650 chipset. “Adelaide” will support the 45nm AMD Opteron™ 4100 Series processor (“Lisbon”) and the 32nm AMD Opteron™ 4200 Series processor (“Valencia”).
Planned for introduction: 1H10
“AMD Velocity”
Market: Multiple devices
What is it? Represents a shift in the company’s design methodology and product introduction cadence. In bringing about the Accelerated Processing Unit era of computing, visual computing technologies will increasingly drive the AMD pace of innovation. The AMD Fusion™ Design Methodology will build on AMD’s already established annual GPU design cycle to achieve a faster innovation pace than AMD previously achieved with a CPU-only development focus. AMD Velocity is designed to deliver performance breakthroughs via teraFLOPS-class GPU compute power in tandem with performance and low-power x86 core options. It is expected to result in clear, compelling platform differentiation for AMD, and the delivery of our best APU on the market every year.
Planned for introduction: Current guiding principle for AMD roadmaps
“Bobcat”
Market: Multiple devices, including notebooks like ultrathins and netbooks.
What is it? A very low-power x86 processor core first featured in the “Ontario” APU primarily aimed at notebook processing in ultrathin and netbook form factors. “Bobcat” is designed to be an extremely small, highly flexible, single threaded x86 core that easily can be scaled up and combined with other IP in SoC configurations.
Planned for introduction: 2011
“Brazos”
Market: Notebook
What is it? Ultrathin notebook and netbook platform and <20W “new market products” platform to include dual-core “Ontario” APU. It will feature DirectX 11-capable graphics..
Planned for introduction: 2011
“Broadway”
Market: Notebook Discrete Graphics
What is it? 40nm Mobility Radeon™ GPU for enthusiast notebooks, with GDDR5 and DirectX 11 graphics.
Planned for introduction: 1H10
“Budapest”
Market: Server
What is it? Quad-Core AMD Opteron™ processor with AM2 Socket for 1P server market.
Introduced: Q208
“Buenos Aires”
Market: Server
What is it? Socket AM3 server platform with SR56x0 chipset supporting the 45nm Quad-Core AMD Opteron™ processor for 1P markets (code-named “Suzuka”).
Introduced: Q209
“Bulldozer”
Market: Server and Client
What is it? A multi-threaded performance-oriented x86 processor core contained in the “Zambezi” processor for client PCs and “Interlagos” and “Valencia” processors for servers. Included in the “Scorpius” desktop PC platform and “Maranello,” “Adelaide,” and “San Marino” server platforms. “Bulldozer” will be a completely new, high performance architecture for the mainstream server, desktop and notebook PC markets that employs a new approach to multithreaded compute performance for achieving advanced efficiency and throughput. “Bulldozer” is designed to give AMD an exceptional CPU option for linking with GPUs in highly scalable, single-chip Accelerated Processing Unit (APU) configurations. “Bulldozer” offers AMD another exceptional CPU option for linking with GPUs in highly scalable, single chip APU configurations.
Planned for introduction: 2011
“Caspian”
Market: Notebook
What is it? A 45nm dual-core notebook processor included in the 2009 Mainstream notebook platform codenamed “Tigris”.
Introduced: 2H09
“Cedar”
Market: Discrete Graphics
What is it? Entry level desktop discrete DirectX 11-capable graphics card.
Planned for introduction: 1H10
“Champlain”
Market: Notebook
What is it? The first AMD quad-core notebook processor, intended for the “Danube” mainstream notebook platform. Includes 2M cache and DDR3 memory support.
Planned for introduction: 1H10
“Conesus”
Market: Notebook
What is it? A dual-core BGA socket notebook processor included in the 2nd generation ultrathin notebook platform.
Introduced: 2H09
“Cypress”
Market: Discrete Graphics
What is it? Enthusiast graphics card, with models branded as the ATI Radeon™ HD 5870 and ATI Radeon™ HD 5850.
Introduced: 2H09
“Danube”
Market: Notebook
What is it? Mainstream notebook platform with DirectX 10.1 IGP and DDR3 memory for high performance with optimum efficiency. Includes DirectX 11 discrete graphics options. This platform, which is designed to offer up to 7 hours of battery life under typical usage scenarios, will bring to market the “Champlain” processor, the first quad-core processors offered by AMD specifically for the notebook market.
Planned for introduction: 1H10
“Dorado”
Market: Desktop
What is it? Mainstream desktop platform that supports socket AM3 dual-core, triple-core and quad-core AMD Athlon™ II processors and includes the RS880P + SB810 chipset.
Planned for introduction: 1H10
“Geneva”
Market: Notebook
What is it? Dual-core 45 nm BGA socket processor with 2M cache and DDR3 memory support for the “Nile” ultrathin notebook platform.
Planned for introduction: 1H10
“Hemlock”
Market: Discrete Graphics
What is it? Targeting ultra high-end enthusiasts, this graphics card includes two “Cypress” GPUs and is expected to be the fastest graphics card in the world when it is introduced later this year.
Planned for introduction: 2H09
“Huron”
Market: Notebook
What is it? A single-core BGA socket notebook processor included in the 1st generation ultrathin notebook platform, formerly codenamed “Yukon”.
Introduced: 1H09
“Interlagos”
Market: Server
What is it? 12- or 16-core 32nm server processor for 2P and 4P markets, based on the new “Bulldozer” processor core. Will carry the AMD Opteron™ 6200 Series processor brand and be supported by the AMD Opteron™ 6000 Series (“Maranello”) platform.
Planned for introduction: 2011
“Istanbul”
Market: Server
What is it? The Six-Core AMD Opteron™ processor that pairs with current Socket F (1207) platforms, as well as recently introduced platforms based on the AMD 56x0 chipsets.
Introduced: 1H09
“Juniper”
Market: Discrete Graphics
What is it? ATI Radeon™ HD 5770 and ATI Radeon™ HD 5750 graphics cards, targeting the price/performance focused consumer.
Introduced: 2H09
“Leo”
Market: Enthusiast Desktop
What is it? Successor of current “Dragon” enthusiast desktop platform technology. “Leo” will feature “Thuban” six-core AM3 processors, new AMD RD890 performance chipsets, and next generation DirectX 11-capable discrete graphics cards from the ATI Radeon™ HD 5000 Family. Leo is expected to offer ultimate performance for immersive gaming with support for ATI Eyefinity technology.
Planned for introduction: 1H10
“Lisbon”
Market: Server
What is it? 4 or 6 core 45nm server processor servicing 1P and 2P markets. Will be branded as the AMD Opteron™ 4100 Series processor and supported by the AMD Opteron™ 4000 Series platform (“San Marino”) or the ultra low-power “Adelaide” platform.
Planned for introduction: 1H10
“Llano”
Market: Notebooks and Desktops
What is it? “Llano” is a 32nm processor, and AMD’s first APU (Accelerated Processing Unit). It is primarily intended for mainstream notebooks and desktops. “Llano” is engineered to deliver impressive visual computing experiences, outstanding performance with low power and long battery life.
Planned for introduction: 2011
“Lynx”
Market: Mainstream Desktop
What is it? Energy-efficient mainstream desktop platform based on “Llano” APUs with multiple processor cores and DDR3 memory, as well as DX11 graphics technology.
Planned for introduction: 2011
“Madison”
Market: Notebook Discrete Graphics
What is it? 40nm Mobility Radeon™ GPU for performance notebooks with GDDR5 and DirectX 11 graphics.
Planned for introduction: 1H10
“Magny-Cours”
Market: Server
What is it? 8 or 12-core 45nm server processor with HyperTransport 3.0 and 4 channels of DDR3 memory, for 2P and 4P markets. Will be branded as the AMD Opteron™ 6100 Series processor and be offered on the AMD Opteron™ 6000 Series platform (“Maranello”).
Planned for introduction: 1H10
“Maranello”
Market: Server
What is it? New AMD Opteron™ 6000 Series platform using a G34 socket with the AMD SR56x0 chipset. The platform is planned to offer DDR3 memory capability and support the 45nm AMD Opteron™ 6100 Series (“Magny-Cours”) and 32nm AMD Opteron™ 6200 Series (“Interlagos”) processors. “Maranello,” is designed to introduce unprecedented leaps in performance-per-watt for AMD Opteron™ processors
Planned for introduction: 1H10
“Nile”
Market: Notebook
What is it: “Nile” is AMD’s third-generation ultrathin notebook platform which features the 45nm dual-core “Geneva” processor using DDR3 memory technology and is designed to enable more than seven hours battery life under typical usage scenarios.
Planned for Introduction: 1H10
“Ontario”
Market: Primarily ultrathin notebooks and netbooks
What is it? Dual-core System on a Chip (SoC) implementation and APU of the upcoming “Bobcat” core for ultrathin notebooks, netbooks and <20W new market products. Ontario is designed to offer a performance PC experience in a low-power design.
Planned for introduction: 2011
“Park”
Market: Notebook Discrete Graphics
What is it? 40nm mainstream Mobility Radeon™ GPU with GDDR5 and DirectX 11 graphics.
Planned for introduction: 1H10
“Redwood”
Market: Discrete Graphics
What is it? Mainstream desktop discrete DirectX 11-capable graphics card.
Planned for introduction: 1H10
“Sabine”
Market: Notebook
What is it? Energy-efficient, mainstream notebook platform based on quad-core “Llano” APUs and supporting DirectX 11 graphics and DDR3 memory.
Planned for introduction: 2011
“San Marino”
Market: Server
What is it? New 1P and 2P server platform suited for large, dense deployments that require power efficiency and flexibility, as well as environments where cost is a key driver. Designed to be ideal for small/medium businesses, as well as web, cloud and infrastructure applications. Will be branded as the AMD Opteron™ 4000 Series platform and will support 4-core and 6-core 45nm AMD Opteron™ 4100 Series processor (“Lisbon”) and the planned 32nm AMD Opteron™ 4200 Series processor (“Valencia”) using the C32 socket and the AMD SR56x0 chipset.
Planned for introduction: 1H10
“Scorpius”
Market: Desktop
What is it? Enthusiast desktop platform based on the “Zambezi” processor (“Bulldozer” x86 core based) with 4-8 cores, DDR3 memory, AM3 socket and next-generation AMD discrete graphics technology.
Planned for introduction: 2011
“Suzuka”
Market: Server
What is it? 45nm Quad-Core AMD Opteron™ processor for 1P server market.
Introduced: 1H09
“Thuban”
Market: Desktop
What is it? New 45-nm socket AM3 enthusiast desktop processors with up to 6 cores for megatasking performance. Will appear within the “Leo” platform.
Planned for introduction: 1H10
“Valencia”
Market: Server
What is it? Six- or eight-core 32nm processor for 1P and 2P markets, based on the new “Bulldozer” processor core. Will be branded as the AMD Opteron™ 4200 Series processor and will be supported by the AMD Opteron™ 4000 Series platform (“San Marino”) or the ultra low-power “Adelaide” platform.
Planned for introduction: 2011
“Zambezi”
Market: Desktop
What is it: 4, 6, or 8-core 32-nm desktop socket AM3 socket processor based on the “Bulldozer” processor architecture for the enthusiast market.
Planned for introduction: 2011
well guess what! Anand is running additional article, and this time without Intel PPT slides ;)Quote:
Originally Posted by Oliverda
http://img2.pict.com/4f/cc/ef/196320...ldozer26bo.jpg
Quote:
Originally Posted by Anand
@ w0mbat
this single post should be put as sticky in AMD room!
"“Bulldozer”
Market: Server and Client
What is it? A multi-threaded performance-oriented x86 processor core contained in the “Zambezi” processor for client PCs and “Interlagos” and “Valencia” processors for servers. Included in the “Scorpius” desktop PC platform and “Maranello,” “Adelaide,” and “San Marino” server platforms. “Bulldozer” will be a completely new, high performance architecture for the mainstream server, desktop and notebook PC markets that employs a new approach to multithreaded compute performance for achieving advanced efficiency and throughput. “Bulldozer” is designed to give AMD an exceptional CPU option for linking with GPUs in highly scalable, single-chip Accelerated Processing Unit (APU) configurations. “Bulldozer” offers AMD another exceptional CPU option for linking with GPUs in highly scalable, single chip APU configurations."
Heh,some things never change with Anand :). I'd say good for him for correcting himself,looks better now(but still can't get rid of that bad aftertaste left by the huge intel slide in the beginning of AMD Fusion article).
He has the b*lls to correct himself.Quote:
Originally Posted by Nedjo
That's good.
Whoaa... big things on the horizon! Can't wait to see what AMD bring out...
Bulldozer bulldozer bulldozer. Damn. Thought if I said it three times it would suddenly appear. We need Bulldozer so badly, 32nm Intel chips are going to wreck Phenom II and Athlon II =\
http://img692.imageshack.us/img692/5...tdayglobal.jpg
Look this guy has many legs!!:D
you think that i3's two cores and two virtual threads can wreck AII X4 four real cores? Not to mention Pentium "G" two cores against AII X3...Quote:
Originally Posted by '[XC
Gulftown is tottaly different -a $1K league to Thuban... so I can't see wrecking there to...
[XBL] on Lliano's specs: http://www.xbitlabs.com/news/cpu/dis...rocessors.html
The Llano 32nm die shot reassures that the 32nm tape out actually happened already and that bulldozer's tape out (if it haven't happened by now) is close too :).
finally someone noticed! and it was in front of us all time on the first page, and first post ;)Quote:
Originally Posted by informal
Yeah,it was weird nobody commented on that fact :). Where is terrace now to tell us that Llano die shot is actually back from the future-a Q3 next year as he told us :p:. AMD seems to be also in time traveling business as of late :D.Quote:
Originally Posted by Nedjo
This is a really good upgrade path for AM3+.
but srry, Clarkdale is for me sucks:down:...Only 2core+HTT. Not so high performance. And nothing without Gulftown new. Maybe in Q3 2010 next quadcore chips at 32nm and later SandyBridge. For next months is only Gulftown dangerous, Clarkdale performance is simillary as Athlon X4 or Intel Quad 8000 with lowers clocksQuote:
Originally Posted by [XC] gomeler
most of athlon II and III with Phenom 5XX 7XX will be out by Core i3.they can not defend own score.so we will wait for bulldozer "http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3674" at least Bulldozer must Crash Core i9.
:D Just wrote this out from the Q&A for my hardware site:Quote:
Originally Posted by informal
Journalist: Rick you mentioned that you will be sampling Bulldozer and Bobcat in 32nm, Fusion products in the first half of 2010. That would suggest that you either have taped out or is close to taping out all those products. Can you give us some sense off where you are in terms of the development on those cores?
Rick Bergman: We don't really give out inner milestones, but we, obviously you know how the semiconductor industry works. You know, June of 2010 is 7 months from now, it takes a few months to build these things so I don't think your comments are off-target at all we are, we're loading up the gun getting ready with our next wave of these fantastic products
Journalist: You mentioned, I think the roadmap for Global Foundries showed that you had, that they were doing 32nm in the second half of 2010. So how do you actually get those built in the first half?
Dirk Meyer: That was a production question.
Emilio Ghiraldi: That's manufacturing ramp, which is consistent with the...
Journalist: So they are doing the tape-outs now?
Rick Bergman: Oh yeah, absolutely and we have running material, we have material.
I think many of the AMD guys on stage were thinking "Will you just shut the :banana::banana::banana::banana: up already?" :D
:up:
Omg !!!
Yeah I know,inq picked up the story too :) :Quote:
Originally Posted by Smartidiot89
http://www.theinquirer.net/inquirer/...d-sample-chips
I expect for terrace to come in and tell us all this is impossible and that Bergam and all the rest actually meant 2012 and it was a slip of the tongue.With that date in mind we should then expect the actual hardware on the shelf by the early 2013 :p:. /sarcasm mode offQuote:
AMD will sample chips early next year
Bulldozer, Bobcat and Fusion previewed
By Nick Farrell
Thursday, 12 November 2009, 12:32
AMD SAID yesterday that will release samples of processor chips built with its Bulldozer and Bobcat CPU cores to computer makers early in 2010.
Senior vice president Rick Bergman said the company wants to give its customers enough time to prepare for product releases at the end of the year.
The plan is that hardware manufacturers can see what is coming so they can gear up to produce products as soon as the processors become available in volume.
The Bobcat core has a sub-1W capable core with four integer and two floating-point instruction pipelines.
The Bulldozer core is a Bobcat with another 4-pipeline integer unit added. Instead of having one combined integer and floating-point scheduler, Bulldozer has two integer schedulers that share a single floating-point scheduler.
Processors incorporating multiple Bulldozer and Bobcat cores will be built on a 32nm silicon on insulator (SOI) process using high-K metal gates.
AMD has also been talking up its Fusion products, which will be a combination of processor and graphics chips, suggesting that it will be making something that Intel can't.
The company claims that Fusion will do its thing by putting the memory controller in charge. Initial fusion cores are going to have both x86 and GPU components, connected via a shared memory controller in the form of a crossbar switch.
Since GPUs need massive memory bandwidth the memory controller is important, particularly if you have multiple CPU cores to work with. AMD needed to come up with a way of feeding several CPU cores with a few hundred GPU cores attached, and apparently it thinks it has.
Pulling this off will be a technological feat in itself and making it work will show that AMD is back in the running. AMD has been falling behind Intel in the chip technology race lately and this has been hurting its bottom line. µ
That might be because they are competitors and anything one of them releases is highly relevant to the other company?
But.........isn't that after the end of the world? :rofl:Quote:
Originally Posted by informal
Who wants one?
http://www.youtube.com/watch?v=Ym7X-...9B4CDA&index=0
Movieman??? :DQuote:
Originally Posted by SocketMan
and me of course! (if it's in my budget)
Is it true that Fusion will have 480 stream processors? That's more than the 3870, and close to a 3870x2! Of course that doesn't mean it's close to that performance since the architecture is different, but the amount itself is impressive.
a 4770 is 640 SPs, at 750Mhz, so if they can get this to run at 1ghz, it would be right with a 4770, which is strong enough to play any game for consoles at 1680x1050 and good eyecandyQuote:
Originally Posted by Vit^pr0n
This Llano Fusion chip is a perfect match for next gen Xbox console :).
yeah i was thinking the same thing. these fusion chips really could create some killer consoles, the ps3 slim v2 could be the size of a ps2 slim with one of these (and i wonder if it will be possible in the future to sli/xfire your consoles...)Quote:
Originally Posted by informal
That is very very impressive. Having that kind of performance added with a 5800 would be amazing.Quote:
Originally Posted by Manicdan
I also think that this is the kind of chip we'll be seeing in the new xbox since ATi is working on that. With the RROD and heat issues of the 360, something tells me MS wants a chip like this. Though I really hope the next-gen consoles will have the capabilities of ATi/Nvidia's latest GPU's at the time ( R1200? GT700? :rofl: ). That would be the time when games make the next giant leap in graphics.
The contender for the most ridiculous article of the year(or even the decade :p:):
Fuad Abazovic's latest and "greatest":
http://www.fudzilla.com/content/view/16425/1/
He has outdone himself with this "piece of news". Newsflash Fudo,you have no idea what you are talking about!:shakes:Quote:
Bulldozer has two quad cores stitched <---[what the hell... :hitself:]
Written by Fuad Abazovic
Friday, 13 November 2009 11:01
Image
Some parts shared
According to Chuck Moore, Corporate Fellow and CTO Technology Development of AMD, the new Bulldozer X86 architecture has “two tightly linked cores.” [After this it all goes downhill and he gets lost in the dark woods of stupidity :shakes: ]
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If you look at the picture above, posted in Chuck's presentation, Bulldozer has two quad cores with an integer scheduler and the two cores share two FPU 128bit FMAC schedulers. <--[:rofl:]
Each int scheduler quad <--[Oh my God :shakes:] has its own L1 cache that talks with L2 shared cache used by both cores and FPU units and finally, the last layer has Shared L3 cache as well as Nortbridge support. (You lost me at 'each'. sub.ed.)
This CPU will be designed to easily interconnect with graphics, but such a product probably won't launch before 2012. AMD claims Bulldozer and Bobcat are two new x86 cores targeting different usage models.
"Bulldozer will be a completely new, high performance architecture for the mainstream server, desktop and notebook PC markets that employs a new approach to multithreaded compute performance for achieving advanced efficiency and throughput. Bulldozer is designed to give AMD an exceptional CPU option for linking with GPUs in highly scalable, single-chip Accelerated Processing Unit (APU) configurations. Bobcat will target the low power, ultrathin PC markets with an extremely small, highly flexible, core that also is designed to be easily scaled up and combined with other IP in APU configurations,” claims AMD.
AMD didn’t save its breath to attack Intel for stitching two cores together, and in two years from now, it plans to stitch two cores that will share some parts. As far as we know 8-core Nehalem EX can get to 8 native cores even at 45nm and we are quite sure that for late 2010 Intel plans to launch an 8-core 32nm Westmere based CPUs. <--- [totally clueless and lost :shakes: ]
AMD plans Bulldozer for desktop and server market in 2011.
There is a Bobcat related article too,not much less ridiculous than this one of course.Enjoy!
The choice for APU's (LIano, Ontario) was SOI GPU or bulk CPU. According to Fuad, AMD has chosen the second possibility. Both should be made in 40 nm bulk with some RV8x0 GPU. Interesting for me.
Thats not news... its already in the history books. :rofl:Quote:
Originally Posted by informal
Oh my goodness... I cannot even begin to grasp how Fuad could have failed this much. Was he in a right state of mind when he wrote that, or is he actually that clueless?
they wont be able to make it clock that much higher just because its on 32nm. remember this is low power. it will also need a wider bus or faster memory to perform as well as a dedicated graphics card like the 4770.Quote:
Originally Posted by Manicdan
Huh? Unless I'm mistaken, I seem to remember Bergman alluding to the fact they're SOI with the comment that the GPU portion is not a risk item on SOI.Quote:
Originally Posted by Behemot
While AMD's future Fusion offering would certainly have cost/size advantages when used in a game console... it's still a year out and I think the next xbox360 revision should prove to be interesting at a sooner date. Also, like chumbucket mentioned, just because it has a decent amount of SPs doesn't mean the performance is the same as it would be for a discrete implementation... there are still issues of TDP and more importantly the memory interface (I really wish they would've leaked some details on the Fusion memory controller :().
Now what I'm waiting for is the point when the GPU portion will be more native and not necessarily require going through a software driver, which AMD seems to acknowledge.
I am interested in this as well. It seems to be a possible conclusion to this GPU + CPU combining trend.Quote:
Originally Posted by rcofell
But it would require a new instruction set to be able to access those GPU functions, hopefully standardized. Otherwise the only way to access the gpu will continue to be through drivers + API.
your right that how good the memory interface is will have a huge impact, but just for the core SP power, it can sure offload alot of power.Quote:
Originally Posted by Chumbucket843
for power consumption, im not sure what to guess. when going low power, generally its for cheap PCs. the gpu part of the core i feel should have no problem reaching 800-900mhz while staying under 40W, and to offer those features in a single chip, for ultra small PCs that can game, id think they pc could sell for 500-600$ and this chip be ~300$ of that. (youd be paying for convenience, more than performance per dollar)
So what is it at AMD as of late thats really got those guys cruising? I mean getting rid of that jackass CEO I'm sure has something to do about it but what else?
All the big business deals are out of the way, merger and GF spinoff, and the design decisions that happened after the merger seem to be paying off.Quote:
Originally Posted by Glow9
Being asset-lite, fabless, seems to have streamlined much of the process.
Probably better management in all departments and I guess it helps that there is that urgency there due to their financial situation.
Remember that the manufacturer and process have changed. I'd say that the odds are that the GPU part will run sub 600 MHz.Quote:
Originally Posted by Manicdan
Two reasons: Power consumption and "excess" gpu power(compared to the memory bandwidth).
16-core Opteron processor codenamed Interlagos--> 8 modules, 16 core. lol
The process is improved over the old one and if the didn't want 'excess' GPU power they would simply put in a smaller GPU instead of wasting die space.Quote:
Originally Posted by Calmatory
Think of bobcat like a quad core atom with a killer igp. It could litterally replace almost 90% of all PC's. I think bobcat has a really bright future imho. Just think of the power a netbook or nettop would have with one of these. You could use these in a nice little HTPC that could actually game pretty decent. It would kick ions butt big time, you wont even need a IGP. Ion will be desroyed, since intel and AMD can do it all in one chip! Whats the point in keeping ion around if it just adds cost and extra power use. Nvidia cant compete in this market without a x86 processor, ion will become extinct.
This!:rolleyes:Quote:
Originally Posted by hurleybird
Besides I think that GPU part will be on separate PLL which means we should get a multiplier option in BIOS to change freq.
For Laptops it will run at low clock, for desktop only TDP will be a limit.
Graphics performance though will be limited by memory subsystem, but there is a chance of mitigating that problem by sideport and giving GPU access to shared L3 cache.
But please not forget that this APU will be targeting a lot of GPGPU tasks where memory bandwidth is not always a problem and 480ALUs will be utilized fully.
I hope we will see 1.2-2GHz APU clocks, if not stock then after some OC for sure :)
Bulldozer's vision in Fred Weber's head(ex AMD fellow back in 2005) ;) :
http://www.scribd.com/doc/7316303/CPU-Aug-05 (page 108)
When asked : "Q :What are the top three items on your dream list of CPU innovations?" ,Mr Weber(a man who actually was a driving force behind the whole Clustered MultiThreading in the first place;look at his presentations back in 2005) responded:
"FW : Well, I’m thinking a lot about the heterogeneous multiprocessing right now. The other area that is of great interest but there isn’t a solution for right now is how to best automatically, whether in hardware or software, use multiple threads in order to speed up programs that are not traditionally parallel. There are a bunch of techniques, such as run-ahead processing, being investigated. But there’s no obvious solution right now. "
Can you see the effects of the above quote in the bulldozer module diagram ? :D
Well, I know, Fuad; but there are some other indicators, like at http://www.anandtech.com/cpuchipsets...spx?i=3673&p=4 last the picture - Brazos is not colored like 65/45/32 nm (and 28 nm is too far away from 2011). Also http://xtreview.com/addcomment-id-64...rocessors.html talks about some possibilities to TSMC test Fusion on 40 nm bulk process.Quote:
Originally Posted by rcofell
AMD always pimped the Bulldozer out to be a single-threaded maniac. The only way I see that happening is if an ENTIRE module (2 cores and all) can process a single thread by itself. Two real cores working as one to chew through a single thread should be interesting. The Integer and floating point performance of a single module should make that interesting.Quote:
Originally Posted by informal
No. I can't see actually.Quote:
Originally Posted by informal
Guys, you are dreaming too much. While it is possible that one core may help to another with execution some instructions when the the second core is saturated (which is really not a common case - isn't it informal who always says that 4-way execution is too much a for single thread :p:) but it really not what "speculative threading" is.Quote:
Originally Posted by Mechromancer
Here is some interesting:
http://arstechnica.com/hardware/news...-bulldozer.ars
If this is the case, then wonder how does AMD planing to be competative with its 4-"core" in the high-end against 4-core Sandy Bridge/Ive Bridge in the main-stream.Quote:
Right now, AMD is referring to each integer scheduler and the pipelines associated with it as a "core," making each Bulldozer module "dual-core." I think this terminology is a huge mistake, and I hope AMD rethinks it.
High end Bulldozer will have 4 modules.Quote:
Originally Posted by kl0012
From my knowledge, Bulldozer will come in flavours of 4-8 modules of 2mini cores each. So, for the very high-end it will compete with Sandy Bridge quite decently.
Are you sure? I guess AMD is taking now SUN Rock route of sharing FP resources between multiple cores (with offload heavy FP calculation to APU in mind).Quote:
Originally Posted by mindfury
Interview with AMD's Fred Weber - The Future of AMD Microprocessors (March 31st, 2005)Quote:
Originally Posted by informal
When Intel announced Hyper Threading, AMD wasn't (publicly) paying any attention at all to TLP as a means to increase overall performance. But now that AMD is much more interested and more public about their TLP direction, we wondered if there was any room for SMT a la Hyper Threading in future AMD processors, potentially working within multi-core designs.
Fred's response to this question was thankfully straightforward; he isn't a fan of Intel's Hyper Threading in the sense that the entire pipeline is shared between multiple threads. In Fred's words, "it's a misuse of resources." However, Weber did mention that there's interest in sharing parts of multiple cores, such as two cores sharing a FPU to improve efficiency and reduce design complexity. But things like sharing simple units just didn't make sense in Weber's world, and given the architecture with which he's working, we tend to agree.
No you probably misunderstood me. 4 way execution has become standard today,and AMD will obviously use it with BD cores. Plus there are a lot of ways second cluster can do a lot of speculative threading work.For example ,look at one of the patents describing what Mr. Weber expressed in the quote(the patent is actually describing a variation of what we now regard as bulldozer module):Quote:
Originally Posted by kl0012
Link to patent(thanks to dresdenboy's blog;you can count 4 or 5 ways to implement various algorithms for speculative threading on bulldozer like module the patent describes,kl0012Enjoy Enjoy;) ):
As for this:Quote:
0026]In certain instances, the processing pipeline 200 may be processing only a single thread. In this case, the instruction dispatch module 210 can be configured to dispatch integer instruction operations associated with the thread to both integer execution units 212 and 214 based on a predefined or opportunistic dispatch scheme. Alternately, the instruction dispatch module 210 can be configured to dispatch integer instruction operations of the single thread to only one of the integer execution units 212 or 214 and the unused integer execution unit can be shut down or otherwise disabled so as to reduce power consumption. The unused integer execution unit can be disabled by, for example, reducing the power supplied to the circuitry of the integer execution unit, clock-gating the circuitry of the integer execution unit, and the like.
[0027]The implementation of multiple integer execution units that execute in parallel and share the same front-end unit 202 facilitates accelerated execution of a single thread through collaboration between the integer execution units. The integer execution units 212 and 214 can be used to implement a run ahead scheme whereby the instruction dispatch module 210 dispatches memory-access operations (e.g., load operations and store operations) to one integer execution unit while dispatching non-memory-access operations to the other integer execution unit. To illustrate, the front-end unit 202 can fetch and decode instructions associated with a thread such that load instructions later in the program sequence of the thread are prefetched and dispatched to one of the integer execution units for execution while the other integer execution unit is still executing non-memory-access instructions at an earlier point in the program sequence. In this way, memory data will already be prefetched and available in a cache (or already in the process of being prefetched) by the time one of the integer execution units prepares to execute an instruction dependent on the load operation.
[0028]Another example of a collaborative use of the integer execution units 202 and 204 is for an eager execution scheme whereby both results of a branch in an instruction sequence can be individually pursued by each integer instruction unit. When the correct branch is determined, the integer instruction unit that was tasked with the branch that ultimately was correct can transfer its state to the other integer instruction unit and both integer instructions can then be used for execution of the program stream of the thread. Table 1 illustrates an example eager execution of instructions of a thread:
TABLE-US-00001 TABLE 1 Eager Execution Example Section Instructions A add r1, r2, r1 cmp r1, r3 jne next B add r3, 3, r6 . . . mov r6, r3 C next: add r3, 6, r1 . . .
[0029]As illustrated by Table 1, instruction section A represents the instruction sequence leading to and including the conditional jump instruction (jne), the instruction section C represents the instruction sequence that follows if the jump is taken, and the instruction section B represents the instruction sequence between the conditional jump instruction and the target of the conditional jump instruction (next). In this example, the front-end unit 202 could dispatch the instruction sequence represented by sections A and B (i.e., the program flow in the event that the jump is not taken) to the integer execution unit 212 and dispatch the instruction sequence represented by sections A and C (i.e., the program flow in the event that the jump is taken) to the integer execution unit 214. In the event that it is ultimately determined that the jump is to be taken, the state of the integer execution unit 214, having been executing the correct path, can be transferred to the integer execution unit 212. Conversely, in the event that that it is ultimately determined that the jump is not to be taken, the state of the integer execution unit 212, having been executing the correct path, can be transferred to the integer execution unit 212. More detailed eager execution implementations are described below with reference to FIGS. 6 and 7.
[0030]As yet another example, the integer execution units 212 and 214 can be used collaboratively to implement a reliable execution scheme for a single thread. In this instance, the same integer instruction operation is dispatched to both integer execution units 212 and 214 for execution and the results are compared by, for example, the thread retirement modules 226 of each integer execution unit. In the event that the results match, the results of the integer instruction operation are deemed reliable and execution of the next instruction operation proceeds. Otherwise, if there is a mismatch between the results of execution of the same integer instruction operation, the results are deemed unreliable and corrective action is taken, such as by issuing an exception or other interrupt, by executing the integer instruction operation again, etc.
Bulldozer "X8" model(4 modules) will have eight 4 issue cores,as I understand it,since every core inside the module will be 4 issue wide(not 2way but 4 way-per AMD's slide;note that bobcat and bulldozer are similar but designed with different goals in mind so a single 2way bobcat "core" may not be the same as one cluster inside a bulldozer module due to different goals for 2 designs- low power and high performance,respectively ).Quote:
Originally Posted by kl002
So ,AMD will have actually an X4(2 module version) to compete with 4 core SandyB. and X8 to compete with 8 core SandyB.(if intel launches anything like that). The possible 8 core SandyB. will have 16 thread support though,so nobody knows how these 8 physical+8 logical cores will go against 8 physical ones in Bulldozer.
remember the cartoon with roadrunner and coyote when coyote reads "water" on the canister with big G A S O L I N E...
well don't know why I've remeber that, but this is how Fuad reads Bulldozer: http://www.fudzilla.com/content/view/16425/1/
last sentience is just brilliant :D and it shows level of Fudo's ignorance in comparing Smithfield with Bulldozer!Quote:
Originally Posted by Fuad
But of course, he just can't sotp there and must conclude his contemplating with news that isn't news:
hehe... Fudo, the legend :)Quote:
Originally Posted by Fudo
Fudo has truely become Otellini's ass-puppet.:D
for a while there i thought i was at amdzone. lol!
heres an interesting thread re: bulldozr/SpMT(Speculative MT).