TSMCs 40nm is actually 45nm

very interesting article...
http://blog.hackingcough.com/2008/04...-5nm-diffe.htm

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Got that? Up until a few weeks ago, Altera thought it was working on a 45nm process. Until someone at TSMC decided that they were better off calling it a 40nm process. It's no big surprise, because the people talking about the self-same process at the International Electron Device Meeting (IEDM) last December also thought of it as a 45nm process. Which kind of makes you wonder just what TSMC claimed to be shipping last autumn when the company said it had shipped 45nm-process wafers to lead customers.

The issue of what constitutes a process node is something that has exercised Kevin Gibb of Chipworks, the Canadian electronics-analysis company. The number we have been using to describe a process node has pretty much lost all meaning. I have to agree with him, as well as Kaizad Mistry of Intel, who said in his talk about Intel's 45nm process at IEDM: "Contacted gate pitch is perhaps the most important [design] rule for density.”

Once upon a time, the number associated with a given process meant how long the transistor gate was. Then, thanks to some optical trickery, everybody worked out that they could reduce the size of the gate, and increase the speed of circuits, by much more than traditional scaling rules. The result was that, by the time the industry hit 90nm, gates were down to less than 60nm in length. At 65nm, you could find devices with gates not much longer than 40nm.

Then, because leakage power was going through the roof, manufacturers slammed the brakes on. Intel's latest devices seem to have gates no shorter than their 65nm predecessors, at around 40nm. TSMC's '40nm' process looks to be in the same ballpark. The company showed a picture of a 30nm p-channel device. However, these tend to be shorter than the n-channel transistors that people tend to base the overall measurement on. Certainly, in the case of both Intel's and TSMC's processes, leakage from n-channel transistors picks up steam from about 38nm down.

If you look at contacted gate pitch - this basically determines how tightly you can pack transistors that you have actually wired up to circuits[ - there is hardly any difference between Intel's 45nm process and what TSMC claims to be its 40nm process. That comes in at 160nm, with TSMC being very slightly wider at 162nm.

So, what we have now is the situation where the chipmakers are going to quote numbers in the hope that everyone thinks, because they chose a smaller number in the press release, they are in the lead.

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iirc going from 65nm to 45nm didnt have as big of an impact as going from 90nm to 65nm, right? this would explain why...

So Intel's 45nm process for Larrabee/Integrated GMA might be better than TSMCs "40nm" process in terms of performance/power.

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Originally Posted by Firestrider

So Intel's 45nm process for Larrabee/Integrated GMA might be better than TSMCs "40nm" process in terms of performance/power.

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I was under the impression that the gate oxide was still somewhat traditional on TSMC and not high-k.

in the end... does it matter?
who cares how "good" a mfc tech is?
a broken design on a good process node is still inferior to a good design on a bad process node... if performance, price performance, power performance are in range, then who cares how advanced the process node is its made in :D

Odd considering that RV740 absolutely destroys (by a factor of about 2) Nehalem in terms of density.

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Originally Posted by hurleybird

Odd considering that RV740 absolutely destroys (by a factor of about 2) Nehalem in terms of density.

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Transistors counted differently, layers and optimizations for speed/density expanded. Not exactly that simple.


The best comparison would be Atom vs Atom on TSMC (licensed).

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Originally Posted by Macadamia

Transistors counted differently, layers and optimizations for speed/density expanded. Not exactly that simple.


The best comparison would be Atom vs Atom on TSMC (licensed)

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Obviously there will be differences, but something as profound as double the transistor density is about more than just the stuff you listed. Also don't forget Nehalem has way more Cache area than RV740, which should be *very* dense.

Atom vs. Atom on TMSC would be a poor comparison since the chip was designed around Intel fabs from the get go. But it would at least let us say something like: 'TMSC is *at least* this many times denser than Intel node.'

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Originally Posted by hurleybird

Obviously there will be differences, but something as profound as double the transistor density is about more than just the stuff you listed. Also don't forget Nehalem has way more Cache area than RV740, which should be *very* dense.

Atom vs. Atom on TMSC would be a poor comparison since the chip was designed around Intel fabs from the get go. But it would at least let us say something like: 'TMSC is *at least* this many times denser than Intel node.'

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Nehalem is less dense than 2 wolfdales. Yet ~90mio less transistors. Atom is less dense than either of them by a very large margin.

Metal layers, layout etc all affects it.

Atom is a factor: 1.88
Nehalem: 2.78
Yorkfield: 3.83
Phenom 2: 2.93
Q8400: 2.78

All 45nm.

There is also no way that RV740 would run at 2-3Ghz and so on. And shader clusters are very dense per design.

Hurley, no one knows. We'll see what density (& other metrics) Intel will pull off when they finally launch Larrabee. If TSMC's advantage cannot be applied to competing processors it's irrelevant, but if Intel really tries to compete with the GPU makers it will get interesting & we'll be able to compare.
According to Hans TSMC's 40nm node would be about twice as dense as Intel's 45nm, while others argue it's all caused by differences in design (CPU vs GPU). Neither is a convincing explanation IMHO. Maybe a combination of the two... or not.
(discussion starting somewhere on this page)

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Originally Posted by Shintai

There is also no way that RV740 would run at 2-3Ghz and so on. And shader clusters are very dense per design.

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VLIW :yepp:.

Another example is perhaps TSMCs 55nm process. RV770 vs RV790. 956mio vs 959mio transistors. Yet 256mm2 vs 282mm2

RV770: 3.73
RV790: 3.40

It is important to not that increasing the density of transistors will increase parasitic capacitances between the various metal layers, interconnects, transistors themselves etc. The higher your capacitances that harder it is to switch quickly and the more power you will consume. So the Nehalem designers probably intentionally spaced their layout so they can achieve high clocks. What have people gotten Nehalem up to? Over 5 GHz or something. The 4790 shader clocks can't go much over 1 GHz I believe. Imagine how crappy Nehalem would be if it came stock at 800 MHz and OCed to 1GHz.

yes, thats a good point... and not only capacitance, heat should also be a factor... im sure the designs are spread to give hot spots some more space between them.

so 790 is 10% bigger than 770? and it clocks over 10% higher...
makes you wonder how high it would clock if theyd double the die size and give their design more space :D

oh and nehalem does 5g on ln2, rv790 does 1g on air...
the diference is still bit if you compare air vs air and ln2 vs ln2 though

4.5g vs 1.0g on air
5.0g vs 1.3g on ln2

ROFL!!!!!!!!!

And everybody (I mean the "intellectual" ones here on XS) were saying that 40nm is a FULL-node shrink from 55nm. I kept on saying that it just did not seem as dramatic as a leap from 65nm to 45nm for CPU's, but they kept on telling me that it's just as dramatic as the 65-45nm shrink.

and who exactly are those "xs intellectuals"? :lol:

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Originally Posted by saaya

and who exactly are those "xs intellectuals"? :lol:

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Not you, no worries! I'm not gonna say exactly who, but the ones who read this will know what I'm talking about.. heh heh :ROTF:

More here:

http://www.brightsideofnews.com/news...are-gone!.aspx

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Since its announcement a year ago, 40nm half-node process faced serious challenges, and tooling companies are expressing their doubt at the "40nm" part, since some customers such as FPGA-maker Altera [ALTR] were told that they're working with TSMC on a 45nm node, and then end up surprised to hear that TSMC is considering them as "a leading 40nm customer".

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Originally Posted by Bo_Fox

More here:

http://www.brightsideofnews.com/news...are-gone!.aspx

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Thats just a pile of donkey poo.

Brightsideofnews=Fudzilla clone.

You can even see the sensationalism in the headline.

And its a Theo story. You knew long before you clicked the link....

I think it's been obvious for quite some time that all processes are not created equally.

Saying that the claimed nm used determines performance is like saying that the faster the rated response time on an lcd, the better it is.

Nice article.

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Originally Posted by saaya

so 790 is 10% bigger than 770? and it clocks over 10% higher...
makes you wonder how high it would clock if theyd double the die size and give their design more space :D

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Now thats funny.. right up until AMD pays $400 for a die.. :D

But it does make one wonder doesnt it, how would such a beast perform in crysis...

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Originally Posted by saaya

very interesting article...
http://blog.hackingcough.com/2008/04...-5nm-diffe.htm

iirc going from 65nm to 45nm didnt have as big of an impact as going from 90nm to 65nm, right? this would explain why...

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Old article, Wrong article.

On the contrary, TSMC's transistor density is very impressive indeed.


Regards, Hans

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Originally Posted by Shintai

Nehalem is less dense than 2 wolfdales. Yet ~90mio less transistors. Atom is less dense than either of them by a very large margin.

Metal layers, layout etc all affects it.

Atom is a factor: 1.88
Nehalem: 2.78
Yorkfield: 3.83
Phenom 2: 2.93
Q8400: 2.78

All 45nm.

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Intel's SRAM density (in your metric) is ~8. So Wolfdale's density is higher
because it has a higher percentage of the die dedicated to cache SRAM.


Regards, Hans

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Originally Posted by saaya

very interesting article...
http://blog.hackingcough.com/2008/04...-5nm-diffe.htm



iirc going from 65nm to 45nm didnt have as big of an impact as going from 90nm to 65nm, right? this would explain why...

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geometries lost lots of its meanings when u talking about <65nm processes.

isn't it a bit early for computex to be at taipei?

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Originally Posted by Bo_Fox

ROFL!!!!!!!!!

And everybody (I mean the "intellectual" ones here on XS) were saying that 40nm is a FULL-node shrink from 55nm. I kept on saying that it just did not seem as dramatic as a leap from 65nm to 45nm for CPU's, but they kept on telling me that it's just as dramatic as the 65-45nm shrink.

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He wasn't wrong...

The take away message is that if you see a headline "new 40nm process chip", the headline tells not much in how the chip will perform. We tend to automatically thing that 40>45>55>65 but we know, even if not that technical, that this is far too simplified. I think we've known that part for a while, but it never hurts to remind forum members just how much this is true, and how it becomes even more true as things get smaller.

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Originally Posted by ahmad

Now thats funny.. right up until AMD pays $400 for a die.. :D

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i doubt that... the actual manufacturing costs for intel and amd cpus are around 30$ as far as i know, for a large chip it might be 60$, maybe 100$, but i dont think its 400$... then again thats how much building a new fab and sustaining the current one actually costs per chip..

but think about it... a less dense, much bigger, high clocked gpu... that might actually be a great way to scale gpus up...
you dont need a new design, you just bloat it up :D just increase the space between the logic and modify it a bit to reach higher clocks...
im not sure how high the design can be clocked without seriously redesigning it, but if thats not an issue and clocks would scale with die size, then a double sized rv770 performing 50% faster would be worth the higher cost i think...

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Originally Posted by ahmad

But it does make one wonder doesnt it, how would such a beast perform in crysis...

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well it would definately be bandwidth limited, thats for sure :D but it should perform very well i suppose...

but the way i always thought of it was this, gpus can be massively parallel without losing any efficiency, cpus cant.
perf per watt efficiency is easier to achieve at low clockspeeds than at high clockspeeds
hence gpus are massively parallel and big, dense chips, while cpus are not that parralel and rather need high performance per core, hence few high clockspeed cores, less dense, smaller chip

it seems out of the 3 ways to improve performance, an architectual improvement is the most tricky and risky approach, the easiest is ramping up clockspeeds or doubling the design making it parrallel.

ramping clockspeeds didnt work for cpus anymore, instead of improving the arch significantly they dodge and go the easy way, multiplying the cores :D

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Originally Posted by Hans de Vries

Old article, Wrong article.
On the contrary, TSMC's transistor density is very impressive indeed.
Regards, Hans

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thanks for clarifying... i wasnt 100% sure since the author doesnt seem to know much about manufacturing tech and just referred to other sources.

well its hard to define a node then, isnt it?
its a mix of density performance and power...
ati and nvidia want performance first, power second and density third i assume, other customers like alterra probable want power first, performance second and density third, and others density first, power second and performance third...

hmmm i really cant think of a way to compare nodes except for using reference designs and then comparing the two. something an sram cell but more complex, and the comparing the perf/power/density graphs

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Originally Posted by vitaminc

isn't it a bit early for computex to be at taipei?

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what do you mean?