X58 Chipset B3 Stepping Changes
Found the changes for B3 here:
http://www.intel.com/Assets/PDF/specupdate/320839.pdf
If you have B2 and are curious what changed in B3, then it looks like the following were either fixed or do not apply to B3:
Quote:
3319486, 3319733: DEVCON2[3:0] and CTOCTRL not accurately set the
completion timeout value.
3319609: Boot-dependent QPI CRC errors
3319688: Some Gen2 endpoints will not complete the training in Gen2 mode.
3319737: MIERRCNT does not properly count persistent SMBus retry failures
and MINNERRST doesn't log the errors (HEDT only)
3319811: EOI to the I/OxAPIC can be blocked
3319755: GTIME upper 32 bits can not be read or written.
3319791: Intel® QuickPath Interconnect (QPI) L0s and L1 Power Management
Link State Fails
3319795:PCI Express* 2.0 L0s Link Recovery Fails
3319874: IOH May Falsely Assert THERMTRIP_N Signal After a Reset Event
3319408: VT-d queue-based invalidation is enabled only when enabled on both
channels (WS only)
3319432: VTd does not support the draining of compatibility-format interrupts
(WS only)
3319452: Hardware applies HPA_LIMIT to upstream memory request when VTd
is disabled (WS only)
3319630: VT-d: Memory read request with AT=11 results in malformed TLP
3319532: VT-d: IOTLB Domain-page-selective invalidation not working
correctly.
3319847: The IOH Ignores Snoop Behavior Bit in VT-d Page Table.
3319819: VT-d reports an Invalidation Queue Error when the Queue size is 7
(HEDT only)
Now I want to know if/when the DX58SO desktop board will include this. The latest revision E29331-503 does not mention this new B3 X58.
Confirmed B3 chipset here...
Quote:
Originally Posted by
003
When the hell are we gonna get some kind of confirmation that there are boards circulating with the B3 stepping??!
Figured id chime in , my P6T7 WS Supercomputer has it for sure :yepp: